9.4 Spice Simulations
1. Input signal amplitudes are between 200 and 2000mV
More detailed analysis of the GS9035A PLL can be done
using SPICE. A SPICE model of the PLL is shown below:
2. The common mode input voltage range is as specified
in the DC Characteristics table.
Commonly used interface examples are shown in
Figures 19 and 20.
PHII
G1
PHIO
IN+
LF
E1
Figure 19 illustrates the simplest interface to the GS9035A.
In this example, the driving device generates the PECL
level signals (800mV amplitudes) having a common mode
input range between 0.4 and 4.6V. This scheme is
recommended when the trace lengths are less than 1in. The
value of the resistors and the DC connection (VCC or
Ground), depends on the output driver circuitry of the
previous device.
2πK
ƒ
IN-
V1
Ns
R
LF
1
C
LF2
R2
C
LF1
NOTE: PHII, PHIO, LF and 1 are node names in the SPICE netlist.
Fig. 18 SPICE Model of PLL
V
or GND
CC
The model consists of a voltage controlled current source
(G1), the loop filter components (RLF, CLF1, and CLF2), a
voltage controlled voltage source (E1), and a voltage
source (V1). R2 is necessary to create a DC path to ground
for Node 1.
DDI
DDI
GS9035A
V1 is used to generate the input phase waveform. G1
compares the input and output phase waveforms and
generates the charge pump current, ΙCP. The loop filter
components integrate the charge pump current to establish
the loop filter voltage. E1 creates the output phase
waveform (PHIO) by multiplying the loop filter voltage by
the value of the Laplace transform (2pKƒ/Ns).
V
or GND
CC
Fig. 19 Simple Interface to the GS9035A
When trace lengths become greater than 1in, controlled
impedance traces should be used. The recommended
interface for differential signals is shown in Figure 20. In this
case, a parallel resistor (RLOAD) is placed near the GS9035A
inputs to terminate the controlled impedance trace. The
value of RLOAD should be twice the value of the
characteristic impedance of the trace. Both traces should
be in a symmetric arrangement and same physical
transmission line dimensions since common-mode signals
or common-mode noise is not terminated. In addition,
series resistors, RSOURCE, can be placed near the driving
chip to serve as source terminations. They should be equal
to the value of the trace impedance. Assuming 800mV
output swings at the driver, RLOAD =100Ω, RSOURCE =50Ω
and ZO = 50Ω.
The netlist for the model is given below. The .PARAM
statements are used to set values for ΙCP, Kƒ, N, and D. ΙCP
is determined by the RVCO resistor and is obtained from
Figure 17.
SPICE NETLIST * GS9035A PLL Model
.PARAM ICP = 165E-6 KF= 90E+6
.PARAM N = 1 D = 0.5
.PARAM PI = 3.14
.IC V(Phio) = 0
.ac dec 30 1k 10meg
RLF 1 LF 1000
CLF1 1 0 15n
CLF2 0 LF 15p
E_LAPLACE1 Phio 0 LAPLACE {V(LF)} {(2*PI*KF)/(N*s)}
G1 0 LF VALUE{D * ICP/(2*pi)*V(Phii, Phio)}
V1 2 0 DC 0V AC 1V
R
SOURCE
SOURCE
Z
O
DDI
DDI
R
GS9035A
LOAD
R
R2 0 1 1g
Z
O
.END
Fig. 20 Recommended Interface for Differential Signals
10. I/O DESCRIPTION
Figure 21 shows the recommended interface when the
GS9035A is driven single-endedly. In this case, the input
must be AC-coupled and a matching resistor (ZO) must be
used.
10.1 High Speed Inputs (DDI/DDI)
DDI/DDI are high impedance inputs which accept
differential or single-ended input drive. Two conditions must
be observed when interfacing to these inputs:
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