acquisition circuit may have to cycle through 5 possible
counter states (depending on initial conditions) to acquire
lock. The nominal value of Tcycle for the GS9035 operating in
a typical SMPTE 259M application is approximately 1.3ms.
A model of the GS9035 PLL is shown below. The main
components are the phase detector, the VCO, and the
external loop filter components.
PHASE
DETECTOR
The GS9035 has a dedicated LOCK output (pin 3)
indicating when the device is locked. It should be noted
that in synchronous switching applications where the
switching time is less than 0.5µs, the LOCK output will NOT
be de-asserted and the data outputs will NOT be muted.
Ø
+
i
VCO
Ι
K
CP
PD
2πK
f
-
Ø
o
Ns
R
LF
LOOP
FILTER
C
LF2
OUTPUT DATA MUTING
C
LF1
The GS9035 internally mutes the SDO and SDO outputs
when the device is not locked. When muted, SDO/SDO are
latched providing a logic state to the subsequent circuit
and avoiding a condition where noise could be amplified
and appear as data. The output data muting timing is
shown in Figure 10.
Fig. 11
The transfer function of the PLL is defined as Øo/Øi and can
be approximated as:
sCLF1RLF + 1
Øo
1
NO DATA TRANSITIONS
DDI
------------------------------------------------------------------------------------------------------------------------
------ =
Øi
L
L
s2CLF2L + s
+ 1
s CLF1
R
LF – ---------- + 1
---------
RLF
RLF
LOCK
Equation 1
where:
VALID
DATA
VALID
DATA
N
L = -------------------
SDO
OUTPUTS MUTED
DICPKƒ
Fig. 10
N is the divider modulus
CLOCK ENABLE
D is the data density (=0.5 for NRZ data)
ICP is the charge pump current in Amps
Kƒ is the VCO gain in Hz/V
When CLK_EN is high, the GS9035 SCO/SCO outputs are
enabled. When CLK_EN is low, the SCO/SCO outputs are
tri-stated and float to VCC. Disabling the clock outputs
results in a power savings of 10%. It is recommended that
the CLK_EN input be hard wired to the desired state. For
applications which do not require the clock output, CLK_EN
should be connected to Ground and the SCO/SCO outputs
This response has 1 zero (wZ) and three poles (wP1, wBW
wP2) where:
,
1
should be connected to VCC
.
wZ = ----------------------
CLF1RLF
STRESSFUL DATA PATTERNS
1
All PLL's are susceptible to stressful data patterns which
can introduce bit errors in the data stream. PLL's are most
sensitive to patterns which have long run lengths of 0's or
1's (low data transition densities for a long period of time).
The GS9035 has been designed to operate with low data
transition densities such as the SMPTE 259M pathological
signal (data transition density = 0.05).
wP1 = --------------------------------------
L
C
LF1RLF – ---------
RLF
RLF
wBW = ---------
L
1
wP2 = ----------------------
CLF2RLF
PLL DESIGN GUIDELINES
The performance of the GS9035 is primarily determined by
the PLL. Thus, it is important that the system designer is
familiar with the basic PLL design equations.
The bode plot for this transfer function is plotted in Figure
12.
9
521 - 69 - 03
GENNUM [ GENNUM CORPORATION ]
