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GS9021 参数 Datasheet PDF下载

GS9021图片预览
型号: GS9021
PDF下载: 下载PDF文件 查看货源
内容描述: EDH协处理器 [EDH Coprocessor]
分类和应用:
文件页数/大小: 26 页 / 196 K
品牌: GENNUM [ GENNUM CORPORATION ]
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PIN CONNECTIONS
CLIP_TRS
FLYWDIS
BLANK_EN
LSB_TOP
BYPASS_EDH
VBLANKS/L
CRC_MODE
V
DD
GND
R/T
RESET
F2
F1
F0
H
V
DIN9
DIN8
DIN7
DIN6
DIN5
DIN4
DIN3
V
DD
GND
DIN2
DIN1
DIN0
PCLKIN
P7
P6
P5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
GS9021
41
TOP VIEW
40
39
38
37
36
35
34
33
17 18 19 20 21 22 23 24 25 26 2728 29 30 31 32
SCL/P4
SDA/P3
A2/P2
A1/P1
A0/P0
R/W
A/D
CS
HOSTIF_MODE
V
DD
GND
S0
S1
FL0
FL1
FL2
GS9021
DOUT9
DOUT8
DOUT7
DOUT6
DOUT5
DOUT4
DOUT3
V
DD
GND
DOUT2
DOUT1
DOUT0
FLAG_MAP
F_R/W
FL4
FL3
PIN DESCRIPTIONS
NUMBER
1-7, 10-12
13
14-16
SYMBOL
DIN[9:0]
PCLKIN
P[7:5]
TYPE
I
I
I/O
Parallel digital video data inputs.
Parallel clock input.
In parallel port mode, these are bits 7:5 of the host interface address/data bus. In
I²C mode, these pins must be set LOW.
In parallel port mode, this is bit 4 of the host interface address/data bus. In I²C
mode, this is the serial clock input for the I²C port.
In parallel port mode, this is bit 3 of the host interface address/data bus. In I²C
mode, this is the serial data pin for the I²C port.
In parallel port mode, these are bits 2:0 of the host interface address/data bus. In
I²C mode, these are input bits which define the I²C slave address for the device.
Parallel port read/write control. When HIGH, the parallel port is configured as an
output (read mode). When LOW, the parallel port is configured as an input (write
mode). In I²C mode, this pin must be set HIGH.
Parallel port address/data bus control. When HIGH, the parallel port is used for
address input. When LOW, the parallel port is used for data input or output. In
I²C mode, this pin must be set LOW.
Parallel port chip select. When CS is LOW and R/W is HIGH, the GS9021 drives
the address/data bus. When CS is LOW and R/W is LOW, the user should drive
the address/data bus. When CS is HIGH, the address/data bus is in a high
impedance state (Hi - Z). In I²C mode, this pin must be set HIGH.
Host Interface mode select. When HIGH, the host interface is configured for I²C
mode. When LOW, the host interface is configured for parallel port mode.
DESCRIPTION
17
SCL/P4
I/O
18
SDA/P3
I/O
19-21
A[2:0]/P[2:0]
I/O
22
R/W
I
23
A/D
I
24
CS
I
25
HOSTIF_MODE
I
4
521 - 65 - 05