The serial data signal is connected to the input pins
(SDI/SDI) either differentially or single-ended. An input
return loss of 20dB at 270 Mb/s has typically been achieved
on the CB9025A characterization board. The input signal
then passes through a variable gain equalizing stage
whose frequency response closely matches the inverse
cable loss characteristic. The variation of the frequency
response with control voltage imitates the variation of the
inverse cable loss characteristic with cable length. The gain
stage provides up to 40dB of gain at 200MHz which
typically results in equalization of greater than 350m at
270Mb/s of Belden 8281 cable.
0.6
0.5
0.4
0.3
0.2
0.1
0
100
200
300
400
500
600
The edge energy of the equalized signal is monitored by a
detector circuit which produces an error signal
corresponding to the difference between the desired edge
energy and the actual edge energy. This error signal is
integrated by an external differential AGC filter capacitor
(AGC+/AGC-) providing a steady control voltage for the
gain stage. As the frequency response of the gain stage is
automatically varied by the application of negative
feedback, the edge energy of the equalized signal is kept
at a constant level which is representative of the original
edge energy at the transmitter.
DATA RATE (Mb/s)
= 0 to 70˚C, V = 4.75 to 5.25V
CC
T
A
Fig. 14 Typical Input Jitter Tolerance (Characterized)
0.600
143Mb/s
0.550
177Mb/s
270Mb/s
0.500
0.450
360Mb/s
0.400
The equalized signal is DC restored, effectively restoring
the logic threshold of the equalized signal to its corrective
level irrespective of shifts due to AC coupling.
540Mb/s
0.350
0.300
0.250
0.200
1.1 Signal Strength Indication/Carrier Detect
The GS9025A incorporates an analog signal strength
indicator/carrier detect (SSI/CD) output indicating both the
presence of a carrier and the amount of equalization
applied to the signal. The voltage output of this pin versus
cable length (signal strength) is shown in Figures 2 and 16.
0
10
20
30
40
50
60
70
TEMPERATURE (C˚)
Fig. 15 Typical IJT vs. Temperature (VCC = 5.0V) (Characterized)
With 0m of cable (800mV input signal levels), the SSI/CD
output voltage is approximately 4.5V. As the cable length
increases, the SSI/CD voltage decreases linearly providing
accurate correlation between the SSI/CD voltage and cable
length.
DETAILED DESCRIPTION
The GS9025A Serial Digital Receiver is a bipolar integrated
circuit containing a built-in cable equalizer and reclocker.
Serial digital signals are applied to either the analog
SDI/SDI or digital DDI/DDI inputs. Signals applied to the
SDI/SDI inputs are equalized and then passed to a
multiplexer. Signals applied to the DDI/DDI inputs bypass
the equalizer and go directly to the multiplexer. The
analog/digital select pin (A/D) determines which signal is
then passed to the reclocker.
5
4
3
CD_ADJ
CONTROL RANGE
Packaged in a 44 pin MQFP, the receiver operates from a
single 5V supply to data rates of 540Mb/s. Typical power
consumption is 575mW.
2
1
0
1. CABLE EQUALIZER
500
150 200
250 300 350 400 450
0
50
100
The automatic cable equalizer is designed to equalize
serial digital data signals from 143Mb/s to 540Mb/s.
CABLE LENGTH (m)
Fig. 16 SSI/CD Voltage vs. Cable Length
9 of 18
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522 - 75 - 05
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