1.
PIN CONNECTIONS
TEST
DATA2
DATA1
DATA0
GND
BUFERR
NC
LOCK
VDDIO
DOUT0
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
GND
DOUT8
DOUT9
AOUTA
AOUTB
WC OUT
NC
VDDIO
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
76
49
77
48
78
47
79
46
80
45
81
44
82
43
83
42
84
41
85
40
86
39
87
GS9023A
38
88
37
89
(TOP VIEW)
36
90
35
91
34
92
33
93
32
94
31
95
30
96
29
97
98
28
99
27
100
26
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
VDDIO
DATA3
DATA4
DATA5
DATA6
DATA7
GND
RE
WE
CS
ADDR3
ADDR2
ADDR1
ADDR0
VDDINT
ANCI
TRS
EDH_INS
MUTE
AM2
AM1
AM0
GND
ACLK
GND
GND
PKTEN
PKT0
PKT1
PKT2
PKT3
PKT4
PKT5
PKT6
PKT7
PKT8
VDDIO
AUXEN
CSB
CSA
UDB
UDA
VFLB
VFLA
SAFB
SAFA
GND
TEST
TEST
VDDINT
GS9023A
VDDINT
VM2
VM1
VM0
DEMUX/MUX
DIN9
DIN8
DIN7
DIN6
DIN5
GND
DIN4
DIN3
DIN2
DIN1
DIN0
VDDINT
NOTE: The GS9023A DOUT[9:0] MSB to LSB convention is compatible with
the GS9022 but reversed with the GS9032 or GS7005.
See Interconnection with GS9032 or GS7005 section.
PIN DESCRIPTIONS
NUMBER
1, 17, 26, 90
2-4
SYMBOL
VDDINT
VM[2:0]
I
TYPE
DESCRIPTION
+3.3V power supply pins for core logic.
Video standard format. Used in conjunction with the TRS pin. VM[2] is the MSB
and VM[0] is the LSB. See Table 1.
Mode of operation. When set HIGH, the GS9023A operates in Demultiplex Mode.
When set LOW, the GS9023A operates in Multiplex Mode.
NOTE: A device reset must be performed when switching between Multiplex and
Demultiplex Modes while the device is powered up.
6-10,12-16
DIN[9:0]
I
Parallel digital video signal input. DIN[9] is the MSB and DIN[0] is the
LSB. The digital video input must contain TRS information.
11, 23, 25, 29,
50, 58, 71, 82,
98, 100
18
GND
Device ground.
5
DEMUX/MUX
I
RESET
I
Device reset. Active low.
NOTE: The video input to output data path will be interrupted during device
reset.
GENNUM CORPORATION
4 of 37
RESET
WC INA
WC INB
AINA
AINB
GND
PCLK
GND
19795 - 6
GENNUM [ GENNUM CORPORATION ]
