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GS9022ACPJE3 参数 Datasheet PDF下载

GS9022ACPJE3图片预览
型号: GS9022ACPJE3
PDF下载: 下载PDF文件 查看货源
内容描述: GENLINXTM GS9022A数字视频串行器 [GENLINXTM GS9022A Digital Video Serializer]
分类和应用:
文件页数/大小: 7 页 / 246 K
品牌: GENNUM [ GENNUM CORPORATION ]
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GS9022ADigitalVideoSerializer-DetailedDeviceDescription  
The GS9022A Serializer is a bipolar integrated circuit used to  
convert parallel data into a serial format according to the  
SMPTE 259M standard. The device encodes both eight and  
ten bit TTL-compatible parallel signals producing serial data  
rates up to 400 Mb/s. It operates from a single five volt supply  
and is packaged in a 28 pin PLCC.  
The charge pump delivers a 'charge packet' to the loop filter  
which is proportional to the system phase error. Internal  
voltage clamps are used to constrain the loop filter voltage  
between approximately 1.8 and 3.4 volts.  
The VCO, constructed from a current-controlled multivibrator,  
features operation in excess of 400 Mb/s and a wide pull  
range (40% of centre frequency).  
Functional blocks within the device include the input latches,  
sync detector, parallel to serial converter, scrambler, NRZ to  
NRZI converter, internal cable driver, PLL for 10 x parallel  
clock multiplication and lock detect.  
VCO Centre Frequency Selection  
The wide VCO pull range allows the PLL to compensate for  
variations in device processing, temperature variations and  
changesinpowersupplyvoltage,withoutexternaladjustment.  
A single external resistor is used to set the VCO current for all  
standards.  
The parallel data (PD0-PD9) and parallel clock (PCKIN) are  
applied via pins 3 through 13 respectively.  
Sync Detector  
The Sync Detector looks for the reserved words 000-003 and  
3FC-3FF, in ten bit hexadecimal, or 00 and FF in eight bit  
hexadecimal, used in the TRS-ID sync word. When the  
occurrence of either all zeros or all ones at inputs PD2-PD9 is  
detected, the lower two bits PD0 and PD1 are forced to zeros  
or ones, respectively. This makes the system compatible with  
eight or ten bit data. For non - SMPTE standard parallel data,  
a logic input, Sync Detect Disable (25) is available to disable  
this feature.  
The C  
pin is used to configure the VCO of the GS9022A  
OSC  
in one of three modes, as shown below:  
C
Mode  
OSC  
0.1µF to GND  
Auto Standard  
ƒ/2 ON  
10k Resistor to VCC  
10k Resistor to GND  
ƒ/2 OFF  
In auto standard mode, the capacitor sets the sweep rate at  
which the VCO toggles between ƒ and ƒ/2.  
Scrambler  
The Scrambler is a linear feedback shift register used to  
pseudo-randomize the incoming serial data according to the  
fixedpolynomial(X +X +1).ThisminimizestheDCcomponent  
in the output serial data stream. The NRZ to NRZI converter  
uses another polynomial (X+1) to convert a long sequence of  
ones to a series of transitions, minimizing polarity effects.  
The ƒ/2 ON and ƒ/2 OFF modes are used to configure the  
GS9022A VCO for single standard operation.  
9
4
Thelockdetectcircuitdisablestheserialdataoutputwhenthe  
loopisnotlocked. TheLockDetectoutputisavailablefrompin  
14 and is HIGH when the loop is locked.  
The true and complement serial data, SDO and SDO are  
available from pins 22 and 23. These outputs will drive  
two 75 co-axial cables with SMPTE level serial digital  
video signals.  
Phase Locked Loop  
The PLL performs parallel clock multiplication and provides  
the timing signal for the serializer. It is composed of  
a phase/frequency detector, charge pump, VCO  
divide-by-ten counter, and a divide by two counter.  
a
,
The phase/frequency detector allows a wider capture range  
and faster lock time than that which can be achieved with a  
phase discriminator alone. The discrimination of frequency  
alsoeliminatesharmoniclocking.Withthistypeofdiscriminator,  
the PLL can be over-damped for good stability without  
sacrificing lock time.  
18325 - 01  
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