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GS9021ACFU 参数 Datasheet PDF下载

GS9021ACFU图片预览
型号: GS9021ACFU
PDF下载: 下载PDF文件 查看货源
内容描述: GENLINX -TM II GS9021A EDH协处理器 [GENLINX -TM II GS9021A EDH Coprocessor]
分类和应用: 消费电路商用集成电路
文件页数/大小: 26 页 / 376 K
品牌: GENNUM [ GENNUM CORPORATION ]
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PIN DESCRIPTIONS  
NUMBER  
SYMBOL  
TYPE  
DESCRIPTION  
28, 29  
S[1:0]  
I/O  
Control bits which select whether FF, AP, or ANC EDH flags are active on the EDH  
flag data port (FL[4:0]). In FLAG_MAP mode, the S[1:0] pins become outputs  
(see device description).  
30-34  
35  
FL[4:0]  
F_R/W  
I/O  
I
EDH flag data port to allow access to the EDH flags.  
Flag port read/write control. When HIGH, FL[4:0] are configured as outputs  
allowing EDH flags to be read from the device. When LOW, FL[4:0] are  
configured as inputs allowing EDH flags to be overwritten into the outgoing EDH  
packet. In FLAG_MAP mode this pin must be set HIGH.  
36  
FLAG_MAP  
I
FLAG_MAP mode enable. When HIGH, FLAG_MAP mode is enabled. When  
LOW, FLAG_MAP mode is disabled.  
37-39, 42-48  
DOUT[9:0]  
O
O
O
O
I
Parallel digital video data outputs.  
Vertical sync indication.  
49  
50  
V
H
Horizontal sync indication.  
51-53  
54  
F[2:0]  
RESET  
R/T  
Field indication. F2 is the MSB.  
Reset. When LOW, the internal control circuitry is reset.  
55  
I
Receive/Transmit mode select. When HIGH, the device operates in receive mode.  
When LOW, the device operates in transmit mode.  
58  
59  
CRC_MODE  
VBLANKS/L  
I
I
CRC_MODE enable. When HIGH, CRC_MODE is enabled. When LOW,  
CRC_MODE is disabled.  
Vertical blanking interval control. For NTSC signals, when VBLANKS/L is set LOW  
the 19 line blanking interval is selected and when set HIGH the 9 line blanking  
interval is selected. For PAL D2 signals, when VBLANKS/L is set LOW the 17 line  
blanking interval is selected and when set HIGH the 7 line blanking interval is  
selected. For PAL component signals VBLANKS/L should be set LOW.  
60  
61  
62  
63  
64  
BYPASS_EDH  
LSB_TOP  
I
I
I
I
I
Bypass EDH control. When HIGH, the device allows the EDH packet to pass  
through unaltered.  
Data output LSB position control. When HIGH, the video data output bus is  
reversed, placing the LSB at pin 48.  
BLANK_EN  
FLYWDIS  
Blanking enable. When LOW, incoming data words are set to appropriate  
blanking levels.  
Flywheel disable. When HIGH, the internal flywheel is disabled. When LOW, the  
internal flywheel is enabled.  
CLIP_TRS  
Clip and TRS correction control. When HIGH, the TRS Blanking, ITU-R-601  
clipping and TRS insertion features are enabled.  
8, 26, 41, 57  
9, 27, 40, 56  
VDD  
Power supply (nominally +5V).  
Ground.  
GND  
5 of 26  
19983 - 1