3.4 Ancillary Checksum Verification
3.6 ANC_DATA
PIN
LOGIC OPR
HOST BIT
ANC_CHKSM
EDH_CHKSM
PIN
LOGIC OPR
HOST BIT
ANC_CHKSM
OR
ANC_DATA
The ANC_DATA signal is set HIGH when an ancillary data
packet is exiting the GS9020A. This pin is asserted from the
start of the first header word through to the end of the
checksum word of the ANC packet, inclusive, as shown in
Figure 10.
For each received ANC packet in the incoming data, the
device compares the calculated checksum value to the
embedded checksum for that ANC packet.
If the
checksum values do not match for any ANC packets within
a field, an error is reported via the ancillary EDH flag in the
EDH packet. In addition, if the ANC_CHKSM input pin or
HOSTIF write table bit is asserted HIGH, the ancillary
checksum correction block is enabled and the checksum in
the ANC packet is replaced with the calculated one. This
update is required to prevent the ANC data error from being
flagged at every downstream EDH chip.
3.7 NO_EDH
PIN
LOGIC OPR
HOST BIT
NO_EDH
NO_EDH
Some input data streams may lack the EDH packet. In such
cases, the NO_EDH output pin or HOSTIF read table bit is
asserted HIGH. If only a few fields lack the EDH packet, the
NO_EDH pin/bit will be asserted only for those fields.
When implementing applications which use the EDH core
(ie. BYPASS_EDH set LOW), ANC_CHKSM will indicate a
downstream FF/AP EDH error when an illegal/non-allowed
(3FCH-3FFH) ANC_CHKSM input value is detected. As
such, these values should not be present in the incoming
data and the corresponding FF/AP EDH errors should not
occur. However, if the user wishes to disable the
ANC_CHKSM function, it can be deactivated by setting
both the ANC_CHSKM pin and the ANC_CHKSM host
interface bit LOW.
In determining if the input data stream contains an EDH
packet, the GS9020A looks for two things. First the
presence of an ANC packet with the header 000 3FF 3FF
1F4 and second that the ANC header is in the right spot for
the video standard detected. The NO_EDH signal is a
logical NAND of these two cases. If either one is false, the
NO_EDH flag is set.
If the chip is receiving ANC EDH flag information through
the flag port or the HOSTIF, then the ANC EDH flag
generated by the ancillary checksum verification block will
be overwritten. However, the additional FF/AP EDH flag will
still appear at the next downstream chip if an illegal
checksum of 3FCH-3FFH was detected and the
ANC_CHKSM function was enabled.
3.8 ERRORED FIELD COUNTER
PIN
LOGIC OPR
HOST BIT
ERRORED FIELD COUNTER
CLR[1:0]
If a checksum error is detected in the EDH packet itself, an
additional separate error flag, EDH_CHKSM is set HIGH in
the HOSTIF read table.
ERROR SENSITIVITY BITS
The device has a 24 bit ERRORED FIELD COUNTER. The
counter increments by one on the occurrence of one or
more error flags in an OUTGOING EDH packet. The error
flags that can increment the counter are user-selectable
through the 16 ERROR SENSITIVITY bits in the HOSTIF
write table. The error flag SENSITIVITY bits are active LOW,
so that if a particular sensitivity bit is set LOW, the counter is
sensitive to errors of that type in the OUTGOING EDH
packet. The EDH_CHKSM sensitivity bit is active HIGH.
3.5 UES Error Flag Updating
In receive mode, a UES flag is set HIGH in the outgoing
EDH packet if the corresponding UES flag was HIGH in the
incoming packet or if the corresponding V bit was LOW.
(For example, if the incoming Active Picture V bit is LOW,
the outgoing Active Picture UES bit will be HIGH). If there is
no EDH packet in the incoming data, all three UES flags
(ANC, AP, FF) are set HIGH.
There are four modes of counter operation. The mode is set
through 2 bits in the HOSTIF write table, denoted CLR1 and
CLR0.
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GENNUM [ GENNUM CORPORATION ]
