4ƒ
sc
DATA
STREAM
T
R
S
T
R
S
T
R
S
ACTIVE VIDEO
& H BLANKING
ACTIVE VIDEO
& H BLANKING
SYNC
DETECT
4:2:2
E
A
V
H
BLNK
E
A
V
H
BLNK
S
A
V
S
A
V
ACTIVE
VIDEO
DATA
STREAM
SYNC
DETECT
PCLK IN
PDN
XXX 3FF 000 000 XXX ••• ••• XXX 3FF 000 000 XXX •••
SYNC
DETECT
Fig. 10 Timing Diagram
+5V
LOOP
+10
LOCKED
L.E.D.
2N4400
0.1
330
82
10k
6x100n
5k
+5V
20
26
6
2,5,21,28,40,41
LOCK SSS SYNC (6x VCC)
7
100
100
100
100
DATA 0
DATA 1
DATA 2
DATA 3
DATA 4
DATA 5
DATA 6
DATA 7
PD0
PDI
DET.
DIS.
8
9
38
39
43
42
DATA
SDO
SDO
PD2
PD3
DATA
10
11
12
13
14
15
PD4
PD5
PD6
PD7
PD8
PD9
CLOCK
CLOCK
SCK
SCK
GS9002A
+5V
DATA 8
DATA 9
CLOCK
16
17
36
35
29
1M
PCK IN
DRS0
DRS1
19
22
*150
*10p
PCK-OUT
PARALLEL
CLOCK OUT
LOOP FILT
CREG
RVCO1 RVCO2 RVCO3 RVCO4 VEE
34
33
32
31
1,4
0.1
18,23
25,27
30,37
44
0.1
10k
10k
1
2
3
4
3.9k
1k
820
4x0.1
COMMON
DATA RATE
SELECT DIP
SWITCH
(SEE TRUTH TABLE,
FIG. 2)
+5V
NOTES: Resistors 1, 2, 3 and 4 are used to set the VCO centre frequency. For 143/177 Mb/s ≈ 6kΩ, 270 Mb/s ≈ 2.7kΩ, 360 Mb/s ≈ 1.8kΩ
All resistors in ohms, all capacitors in microfarads unless otherwise stated. represent test points.
*
This RC network is used to slow down fast PCLK risetimes ( ≤ 500ps). It is not required if risetimes exceed 500ps.
Fig. 11 GS9002A Test Circuit
8 of 11
24149 - 1
GENNUM [ GENNUM CORPORATION ]
