GENLINX
™
GS9000C
Serial Digital Decoder
DATA SHEET
FEATURES
• fully compatible with SMPTE 259M
• decodes 8 and 10 bit serial digital signals for data
rates to 370Mb/s
• pin and function compatible with GS9000S, GS9000
and GS9000B
• 325mW power dissipation at 270MHz clock rates
• incorporates an automatic standards selection
• function with the GS9005A Receiver or GS9015A
Reclocker
• Pb-free and Green
• operates from single +5 or -5 volt supply
• enables an adjustment-free Deserializer system when
used with GS9010A and GS9005A or GS9015A
• 28 pin PLCC packaging
APPLICATIONS
•
•
4ƒ
SC
, 4:2:2 and 360Mb/s serial digital interfaces
Automatic standards select controller for serial routing
and distribution applications using GS9005A Receiver
or GS9015A Reclocker
DEVICE DESCRIPTION
The GS9000C is a CMOS integrated circuit specifically
designed to deserialize SMPTE 259M serial digital signals
at data rates to 370Mb/s.
The device incorporates a descrambler, serial to parallel
convertor, sync processing unit, sync warning unit and
automatic standards select circuitry.
Differential pseudo-ECL inputs for both serial clock and
data are internally level shifted to CMOS levels. Digital
outputs such as parallel data, parallel clock, HSYNC, Sync
Warning and Standard Select are all TTL compatible.
The GS9000C is designed to directly interface with the
GS9005A Reclocking Receiver to form a complete SMPTE-
serial-in to CMOS level parallel-out deserializer. The
GS9000C may also be used with the GS9010A and the
GS9005A to form an adjustment-free receiving system
which automatically adapts to all serial digital data rates.
The GS9015A can replace the GS9005A in GS9000C
applications where cable equalization is not required.
The GS9000C is packaged in a 28 pin PLCC and operates
from a single 5 volt, ±5% power supply.
GS9000C
NOT RECOMMENDED FOR NEW DESIGNS - SEE GS9000D
GS9000C
SERIAL DATA IN
SERIAL DATA IN
LEVEL
SHIFT
30 - BIT
SHIFT REG
PARALLEL DATA
OUT (10 BITS)
DESCRAMBLER
SP
SERIAL CLOCK IN
SERIAL CLOCK IN
LEVEL
SHIFT
SCLK
SYNC DETECT
(3FF 000 000 HEX)
Sync
Word
Boundary
PARALLEL
TIMING
GENERATOR
PARALLEL CLOCK
OUT
SYNC CORRECTION
ENABLE
SYNC CORRECTION
Sync Error
HSYNC OUTPUT
SYNC WARNING
CONTROL
SYNC WARNING
(Schmitt Trigger
Comparator)
AUTO STANDARD SELECT
SYNC WARNING
FLAG
STANDARDS SELECT
CONTROL
OSC
2 BIT
COUNTER
Hsync Reset
SS0
SS1
FUNCTIONAL BLOCK DIAGRAM
Revision Date: November 2007
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com
www.gennum.com
Document No. 10326 - 4
GENNUM [ GENNUM CORPORATION ]
