DETAILED DESCRIPTION
The GS7025 Serial Digital Receiver is a bipolar integrated
circuit containing a built-in cable equalizer and reclocker.
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4
Serial digital signals are applied to either the analog
SDI/SDI or digital DDI/DDI inputs. Signals applied to the
SDI/SDI inputs are equalized and then passed to a
multiplexer. Signals applied to the DDI/DDI inputs bypass
the equalizer and go directly to the multiplexer. The
analog/digital select pin (A/D) determines which signal is
then passed to the reclocker.
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2
CD_ADJ
CONTROL RANGE
1
0
Packaged in a 44 pin MQFP, the receiver operates from a
single 5V supply at a data rate of 270Mb/s.
500
150 200
250 300 350 400 450
0
50
100
CABLE LENGTH (m)
Fig. 8 SSI/CD Voltage vs. Cable Length
1. CABLE EQUALIZER
The automatic cable equalizer is designed to equalize a
serial digital data rate of 270Mb/s.
When the signal strength decreases to the level set at the
"Carrier Detect Threshold Adjust" pin, the SSI/CD voltage
goes to a logic "0" state (0.8 V) and can be used to drive
other TTL/CMOS compatible logic inputs. In addition, when
loss of carrier is detected, the SDO/SDO outputs are muted
(set to a known static state).
The serial data signal is connected to the input pins
(SDI/SDI) either differentially or single-endedly. The input
signal passes through a variable gain equalizing stage
whose frequency response closely matches the inverse
cable loss characteristic. In addition, the variation of the
frequency response with control voltage imitates the
variation of the inverse cable loss characteristic with cable
length. The gain stage provides up to 35dB of gain at
135MHz which typically results in equalization of greater
than 350m of Belden 8281 cable at 270Mb/s.
1-2. Carrier Detect Threshold Adjust
This feature has been designed for use in applications such
as routers where signal crosstalk and circuit noise cause
the equalizer to output erroneous data when no input signal
is present. The use of a Carrier Detect function with a fixed
internal reference does not solve this problem since the
signal to noise ratio on the circuit board could be
significantly less than the default signal detection level set
by the on chip reference. To alleviate this problem, the
GS7025 provides a user adjustable threshold to meet the
unique conditions that exist in each user's application.
Override and internal default settings have also been
provided to give the user total flexibility.
The edge energy of the equalized signal is monitored by a
detector circuit which produces an error signal
corresponding to the difference between the desired edge
energy and the actual edge energy. This error signal is
integrated by an external differential AGC filter capacitor
(AGC+/AGC-) providing a steady control voltage for the
gain stage. As the frequency response of the gain stage is
automatically varied by the application of negative
feedback, the edge energy of the equalized signal is kept
at a constant level which is representative of the original
edge energy at the transmitter.
The threshold level at which loss of carrier is detected is
adjustable via external resistors at the CD_ADJ pin (see
Figure 4). The control voltage at the CD_ADJ pin is set by a
simple resistor divider circuit (see Typical Application
Circuit). The threshold level is adjustable from 200m to
350m. By default (no external resistors), the threshold is
typically 320m. In noisy environments, it is not
recommended to leave this pin floating. Connecting this pin
to VEE disables the SDO/SDO muting function and allows for
maximum possible cable length equalization.
The equalized signal is also DC restored, effectively
restoring the logic threshold of the equalized signal to its
corrective level irrespective of shifts due to AC coupling.
1-1. Signal Strength Indication/Carrier Detect
The GS7025 incorporates an analog signal strength
indicator/carrier detect (SSI/CD) output indicating both the
presence of a carrier and the amount of equalization
applied to the signal. The voltage output of this pin versus
cable length (signal strength) is shown in Figure 2 and
Figure 8.
1-3. Output Eye Monitor Test
The GS7025 also provides an 'Output Eye Monitor Test'
(OEM_TEST) which allows the verification of signal integrity
after equalization, prior to reslicing. The OEM_TEST pin is
an open collector current output that requires an external
50Ω pullup resistor. When the pullup resistor is not used,
the OEM_TEST block is disabled and the internal
OEM_TEST circuit is powered down. The OEM_TEST
With 0m of cable (800mV input signal levels), the SSI/CD
output voltage is approximately 4.5V. As the cable length
increases, the SSI/CD voltage decreases linearly providing
accurate correlation between the SSI/CD voltage and cable
length.
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GENNUM CORPORATION
522 - 80 - 00
GENNUM [ GENNUM CORPORATION ]
