5. OUTPUT DATA MUTING
1. Input signal amplitudes are between 200 and 2000mV.
The GS7025 internally mutes the SDO and SDO outputs
when the device is not locked. When muted, SDO/SDO are
latched providing a logic state to the subsequent circuit
and avoiding a condition where noise could be amplified
and appear as data.
2. The common mode input voltage range is as specified
in the DC Characteristics table.
Commonly used interface examples are shown in Figures
14 to 16.
The output data muting timing is shown in Figure 12.
Figure 14 illustrates the simplest interface to the GS7025
digital inputs. In this example, the driving device generates
the PECL level signals (800mV amplitudes) having a
common mode input range between 0.4 and 4.6V. This
scheme is recommended when the trace lengths are less
than 1in. The value of the resistors depends on the output
driver circuitry.
NO DATA TRANSITIONS
DDI
LOCK
VALID
DATA
VALID
DATA
OUTPUTS MUTED
SDO
DDI
GS7025
DDI
Fig. 12 Output Data Muting Timing
6. CLOCK ENABLE
When CLK_EN is high, the GS7025 SCO/SCO outputs are
enabled. When CLK_EN is low, the SCO/SCO outputs are
placed in a high Z state and float to VCC. Disabling the
clock outputs results in a power savings of 10%. It is
recommended that the CLK_EN input be hard wired to the
desired state. For applications which do not require the
clock output, connect CLK_EN to Ground and connect the
Fig. 14
When trace lengths become greater than 1in, controlled
impedance traces should be used. The recommended
interface is shown in Figure 15. In this case, a parallel
resistor (RLOAD) is placed near the GS7025 inputs to
terminate the controlled impedance trace. The value of
RLOAD should be twice the value of the characteristic
impedance of the trace. In addition, place series resistors
SCO/SCO outputs to VCC
.
7. STRESSFULL DATA PATTERNS
(RSOURCE
) near the driving chip to serve as source
terminations. They should be equal to the value of the trace
impedance. Assuming 800mV output swings at the driver,
All PLL's are susceptible to stressful data patterns which
can introduce bit errors in the data stream. PLL's are most
sensitive to patterns which have long run lengths of 0's or
1's (low data transition densities for a long period of time).
The GS7025 is designed to operate with low data transition
densities such as the SMPTE 259M-C pathological signal
(data transition density = 0.05).
RLOAD = 100Ω, RSOURCE = 50Ω and ZO = 50Ω.
R
SOURCE
Z
O
DDI
R
GS7025
LOAD
R
SOURCE
DDI
Z
O
8. I/O DESCRIPTION
Fig. 15
8-1. High Speed Analog Inputs (SDI/SDI)
Figure 16 shows the recommended interface when the
GS7025 digital inputs are driven single-endedly. In this
case, the input must be AC-coupled and a matching
resistor (Zo) must be used.
SDI/SDI are high impedance inputs which accept
differential or single-ended input drive.
Figure 13 shows the recommended interface when a single-
ended serial digital signal is used.
DDI
10nF
10nF
75
Z
GS7025
O
SDI
SDI
DDI
75
GS7025
113
Fig. 16
Fig. 13
8-2. High Speed Digital Inputs (DDI/DDI)
When the DDI and the DDI inputs are not used, saturate
one input of the differential amplifier for improved noise
immunity. To saturate, connect either pins 44 and 1 or pins
2 and 3 to VCC. Leave the other pair floating.
DDI/DDI are high impedance inputs which accept
differential or single-ended input drive. Two conditions must
be observed when interfacing to these inputs:
11
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