1.2 Pin Descriptions
Table 1-1: Pin Descriptions
Pin
Name
Timing
Type
Description
Number
1
REG_VDD
AGND
–
–
–
–
Power
Power
Power
Input
Positive power supply connection for the internal voltage regulator.
Connect to filtered +3.3V DC.
2, 6, 9, 26,
30, 31, 40
Ground connection for analog blocks and IOs. Connect to clean analog
GND.
3
PD_VDD
Positive power supply connection for the phase detector. Connect to
filtered +1.8V DC.
4, 5
CLKIN, CLKIN
CLOCK SIGNAL INPUTS
Signal levels are CML/LVDS compatible.
A differential clock input signal is applied to these pins.
7
8
IN_VDD
–
–
Power
Input
Positive power supply connection for the single-ended and differential
input clock buffers. Supplies CLKIN_SE. Connect to filtered +1.8V DC.
CLKIN_SE
CLOCK SIGNAL INPUT
Signal levels are LVCMOS compatible.
A single-ended video clock input signal is applied to this pin.
10
11
RESET
IPSEL
Non
synchronous
Input
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
See Section 3.8.1 for operation.
Non
CONTROL SIGNAL INPUT
synchronous
Signal levels are LVCMOS compatible.
Selects which input clock is cleaned by the device.
See Section 3.2.3 for operation.
12, 20, 22
13
GND
–
Power
Input
Ground connection for digital blocks and IO’s. Connect to GND.
BYPASS
Non
CONTROL SIGNAL INPUT
synchronous
Signal levels are LVCMOS compatible.
See Manual Bypass Section 3.4.2.
14
AUTOBYPASS
Non
Input
CONTROL SIGNAL INPUT
synchronous
Signal levels are LVCMOS compatible.
Selects the bypass mode of the device.
See Manual Bypass Section 3.4.2.
15
D_VDD
–
Power
Input
Positive power supply connection for digital block. Connect to filtered
+1.8V DC. The digital block includes pins 10 - 21.
17, 16
FCTRL1, FCTRL0
Non
CONTROL SIGNAL INPUTS
synchronous
Signal levels are LVCMOS compatible.
Selects the frequency mode of the device.
See Section 3.4.1 for operation.
GS4915 ClockCleaner™
Data Sheet
6 of 27
39145 - 5
June 2009
GENNUM [ GENNUM CORPORATION ]
