Table 2-2: AC Electrical Characteristics (Continued)
VDD = 1.8V 5ꢀ, TA = 0ºC to 70ºC, unless otherwise shown
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Notes
Output Jitter
–
–
–
–
–
100kHz to 10MHz
Unfiltered
–
–
20
40
60
100
–
–
–
ps
ps
ps
ps
ꢀ
ꢀ
–
–
–
–
–
–
Differential Output
Output Jitter
100kHz to 10MHz
Unfiltered
–
–
Single-ended Output
–
–
Output Duty Cycle
Differential output
45
40
55
60
Single-ended
output
–
Differential Clock Output Rise / Fall Time
–
–
100Ω diff. load
–
–
500
–
–
ps
ps
–
–
Single-ended Clock Output Rise / Fall
Time
10 pF load
1200
Input Clock Frequency
Output Clock Frequency
Lock Detect Time
–
–
–
12
12
–
–
–
–
165
165
500
MHz
MHz
us
–
–
–
–
tLOCKD
Within 300ppm of
reference
frequency
Unlock Detect Time
tUNLOCKD
Within 700ppm of
reference
–
–
500
us
–
frequency
Lock Time
tLOCK
–
–
–
–
–
1
–
s
2
–
Device Latency
Differential in,
Differential out,
SKEW_EN = LOW
1.2
ns
Differential in,
Differential out,
SKEW_EN = HIGH
–
–
–
–
1.2 -
–
–
–
–
ns
ns
ns
ps
–
–
–
3
T
out/4
Single ended in,
single ended out,
SKEW_EN = LOW
3.5
Single ended in,
single ended out,
SKEW_EN = HIGH
3.5 -
T
out/4
Device Latency Difference
NOTES:
–
–
750
1. One UI refers to one cycle of the input CLK.
2. Assuming power up has already occurred.
3. Difference between cleaning and bypass modes.
GS4915 ClockCleaner™
Data Sheet
11 of 27
39145 - 5
June 2009
GENNUM [ GENNUM CORPORATION ]
