ASR_SEL[2:0]
VID_STD[5:0]
X1
X2
GENLOCK
LOCK_LOST
REF_LOST
27MHz
Input Reference
Rate Identification
and Control
ref_rate
Flywheel and Video
Timing Generator
user[4:1]
AFS
10FID
DE
F digital
F sync
V blanking
V sync
H blanking
H sync
TIMING_OUT_8
TIMING_OUT_7
TIMING_OUT_6
Crosspoint
TIMING_OUT_5
TIMING_OUT_4
TIMING_OUT_3
TIMING_OUT_2
TIMING_OUT_1
Clock Synthesis
and Control
PCLK1
Clock
Phase
Adjust
pclk
Video Clock
Divide
3x Video Clock
Delay Adjust
PCLK2
PCLK3
PCLK3
aclk_512
aclk_384
Audio Clock
Divide
ACLK1
ACLK2
ACLK3
HSYNC
VSYNC
FSYNC
10FID
Application Programming Interace
SDOUT_TDO
JTAG/HOST
GS4911B Functional Block Diagram
GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
SCLK_TCLK
SDIN_TDI
CS_TMS
2 of 119
GENNUM [ GENNUM CORPORATION ]
