GS4901B/GS4900B Preliminary Data Sheet
3.7 Clock Synthesis
The clock synthesis circuit generates the video clocks based on the VID_STD[5:0]
pins and host register settings. In the GS4901B, the clock synthesis circuit also
generates the audio clock signals based on the ASR_SEL[2:0] pins and host
register settings.
The generated video and audio clocks may be further divided and are presented to
the application layer via pins PCLK1-PCLK3 and ACLK1-ACLK3 respectively.
3.7.1 Video Clock Synthesis
The video clock generator is referenced to an internal crystal oscillator and is
responsible for generating the PCLK output signals.
The crystal oscillator requires an external 27MHz crystal connected to pins X1 and
X2, or can be driven at LVTTL levels from an external 27MHz source connected to
X1. These two configurations are shown in Figure 1-1.
Four different video sample clock rates may be selected using the VID_STD[5:0]
pins of the device. Section 1.4 on page 20 lists the video formats available using
the VID_STD[5:0] pins.
If desired, the external VID_STD[5:0] pins may be ignored by setting bit 1 of the
Video_Control register, and the video standard may instead be selected via the
VID_STD[5:0] register of the host interface (see Section 3.10.3 on page 66).
Although the external VID_STD[5:0] pins will be ignored, they should not be left
floating.
Once the video clock has been generated, it will be presented to the application
layer via the PCLK1 to PCLK3 pins. By default, each of the 3 video clock outputs
will produce the generated fundamental clock frequency. However, it is possible to
select other rates for each PCLK output by programming the PCLK_Phase/Divide
registers beginning at address 2Ch of the host interface (see Section 3.10.3 on
page 66).
Each PCLK output may be individually programmed to provide one of the following:
•
•
•
PCLK fundamental frequency
Fundamental frequency /2
Fundamental frequency /4
When all six VID_STD[5:0] pins are set LOW, the video clocks will be disabled.
PCLK1 and PCLK2 will go LOW and PCLK3/PCLK3 will be high impedance.
NOTE: If the PCLK divider bits of registers 2Ch - 2Eh are set to enable a divide by
2 or divide by 4, the resultant divided clock will align with the falling edge of the
output H Sync timing signal either on its rising or falling edge.
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