GS4901B/GS4900B Preliminary Data Sheet
Table 3-2: Ambiguous Standard Identification
Number Standard
H
16_H
(27MHz
Clocks)
V (lines)
F (lines)
Amb_Std_Sel[10:0]
(27MHz
Clocks)
1
2
1920x1080/60/2:1 interlace (25)
800
800
12800
12800
12800
12813
12813
12813
15360
15360
27456
27456
27456
27456
27648
27648
27648
27648
RSVD
13728
562.5
562.5
562.5
562.5
562.5
562.5
562.4
562.4
262.5
262.5
262.5
262.5
312.5
312.5
312.5
312.5
RSVD
525
1125
1125
1125
1125
1125
1125
1125
1125
525
X X X X X X X X X 0 0
X X X X X X X X X 0 1
X X X X X X X X X 1 0
X X X X X X X 0 0 X X
X X X X X X X 0 1 X X
X X X X X X X 1 0 X X
X X X X X 0 0 X X X X
X X X X X 0 1 X X X X
X X X 0 0 X X X X X X
X X X 0 1 X X X X X X
X X X 1 0 X X X X X X
X X X 1 1 X X X X X X
X 0 0 X X X X X X X X
X 0 1 X X X X X X X X
X 1 0 X X X X X X X X
X 1 1 X X X X X X X X
0 X X X X X X X X X X
1 X X X X X X X X X X
1920x1080/30/PsF (30)
1920x1035/60/2:1 interlace (19)
1920x1080/59.94/2:1 interlace (26)
1920x1080/29.97/PsF (32)
1920x1035/59.94/2:1 interlace (20)
1920x1080/50/2:1 interlace (27)
1920x1080/25/PsF (34)
800
800.8
800.8
800.8
960
3
4
960
601 525 / 2:1 interlace (3)
1716
1716
1716
1716
1728
1728
1728
1728
RSVD
858
720x486/59.94/2:1 interlace (7)
4fsc 525 / 2:1 interlace (1)
601 - 18MHz 525/2:1 interlace (5)
601 625 / 2:1 interlace (4)
525
525
525
5
6
625
720x576/50/2:1 interlace (8)
Composite PAL 625/2:1/25 (2)
601 - 18MHz 625/2:1 interlace (6)
RSVD
625
625
625
RSVD
525
720x483/59.94/1:1 progressive (9)
‘X’ signifies ‘don’t care.’ The X bit will be ignored when determining which standard to select in each of the 6 groups above.
NOTE: When the SD input reference format of 720x483/59.94/1:1 (VID_STD = 9) is applied to the input, the user must set bit [15] of the of the
Amb_Std_Sel register address to '1' before the device will recognize this reference.
3.5.3 Behaviour on Loss and Re-acquisition of the Reference Signal
By default, the GS4901B/GS4900B will ignore one missing H pulse on the HSYNC
pin and will continue to operate in Genlock mode (although the LOCK_LOST pin
will temporarily be set HIGH). This behaviour is controlled by the Run_Window bits
of register address 24h.
If there are two consecutive missing H pulses on the HSYNC input pin, the
REF_LOST and LOCK_LOST pins will both go HIGH and the device will enter
Freeze mode. An internal flywheel ensures the selected output clock and timing
signals maintain their previous phase and frequency and continue to operate
without glitches.
The VSYNC and FSYNC signals are not monitored in Genlock mode; loss of signal
on these pins will not affect the operation of the device.
NOTE 1: If the input reference is removed and re-applied, all line-based timing
outputs will be inaccurate for up to one frame for all output standards.
37703 - 0 April 2006
44 of 95
GENNUM [ GENNUM CORPORATION ]
