SIGNAL DETECT AND OUTPUT MUTE
Assuming that the sync separator is in steady state operation
with a valid input signal, all outputs will be enabled. Removal
of the input signal, or a significant change in the input signal
frequency,willcauseaninternalprobationtimertobetriggered.
Internal to the GS4882 and GS4982 is a robust video signal
detection circuit. This circuit provides a reliable control signal
that will enable the sync separator outputs only when a valid
video signal is present. When the input signal is not valid, the
outputs are muted and stay in a logic high state.
While on probation, the sync separator outputs remain
enabled and separated sync is still produced. If a valid input
signal is not returned to the system before the probation time
expires (typically 2.5 ms), all outputs will be muted to logic
high state. Should a valid signal return during the probation
period, and eight lines be received before the probation time
expires, device outputs will remain enabled. Once device
outputs are muted, the device must receive 8 valid lines of
video at the correct horizontal frequency before the outputs
are re-enabled.
The GS4882 and GS4982 differentiate between valid and in-
valid input signals by feeding the horizontal sync information
intoafrequencytovoltageconverter. Thehorizontalscanrate
of the input signal is then compared to an expected input
signal horizontal scan rate. With RSET=227 kΩ, the sync
separator will typically define a valid input signal as one with
a horizontal frequency of 15.7 4 kHz.
CLAMP
CLAMP
CLEN
HORIZONTAL
WINDOW
WINDOW
VSC
+
-
COMPOSITE
SYNC OUTPUT
(Pin 1)
-
+
VIDEO
INPUT
(Pin 2)
2
ND ORDER
BESSEL
BESSEL
FILTER
ND ORDER
-
FILTER
INTEGRATED
INTEGRATED
HOLD
HOLD
2
+
R
R
MUTE
0.1µ
SIGNAL
50%
POINT
-
DETECT
+
V
HC
WINDOWING
V
SC
FAULT
FAULT
HANDLING
HANDLING
D
G
Q
Q
ODD / EVEN
OUTPUT
(Pin 7)
CIRCUIT
D
Q
Q
CLK
NO SYNC
VERTICAL SYNC
OUTPUT
D
Q
Q
VERTICAL
(PIN 3)
V
VOLTAGE
REGULATOR
DETECTOR
CC
(Pin 8)
CLK
BACK PORCH
OUTPUT
BPEN
(Pin 5)
BACK PORCH
DETECTOR
R
SET
TIMING
CURRENTS
(Pin 6)
227k
0.1µ
Fig. 6 GS4882 Block Diagram
CLAMP
WINDOW
CLEN
HORIZONTAL
VSC
+
-
-
HORIZONTAL
(Pin 1)
+
VIDEO
INPUT
(Pin 2)
2
ND ORDER
BESSEL
FILTER
-
INTEGRATED
HOLD
+
R
R
MUTE
0.1µ
SIGNAL
DETECT
50%
POINT
-
VHC
+
WINDOWING
CIRCUIT
FAULT
HANDLING
VSC
D
G
Q
ODD / EVEN
OUTPUT
(Pin 7)
D
Q
Q
Q
CLK
NO SYNC
VERTICAL SYNC
OUTPUT
D
Q
Q
VERTICAL
(PIN 3)
V
VOLTAGE
REGULATOR
DETECTOR
CC
(Pin 8)
CLK
BACK PORCH
OUTPUT
BPEN
(Pin 5)
BACK PORCH
DETECTOR
R
SET
TIMING
CURRENTS
(Pin 6)
227k
0.1µ
Fig. 7 GS4982 Block Diagram
521 - 61 - 01
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GENNUM [ GENNUM CORPORATION ]
