(V = 5 V, R
= 680 kΩ, T = 25° C, unless otherwise specified)
A
GS1881 ELECTRICAL CHARACTERISTICS
CC
SET
PARAMETER
CONDITIONS
MIN
TYP
5
MAX
13.2
6.5
UNITS
V
Supply Voltage
4.5
Supply Current
Outputs at Logic 1
VCC = 5 V
VCC = 12 V
-
-
4.6
5.0
mA
7.0
mA
Video Input (Pin 2)
(a) Signal Level
VCC = 5 V
0.5
500
9
-
4
850
13
Vp-p
µA
µA
µA
µs
(b) Clamp Current
Charge
650
11
Discharge - normal
- Nosync flag raised
65
64
-
95
115
130
-
(c) Delay to raising of Nosync flag Video input held high
(d) Sync Tip Clamp Voltage
95
1.55
77
V
Sync Slice Level
Relative to sync tip clamp voltage
70
1.14
84
mV
V
RSET Pin Reference Voltage (Pin 6) See Note 1
1.24
1.34
Composite Sync Out (Pin 1)
Delay from Video
See Note 2
40
60
80
ns
C
C
= 15p
= 15p
L
L
Back Porch Pulse Out (Pin 5)
(a) Delay from Rising
Edge of Sync
400
2.0
500
2.5
650
3.2
ns
(b) Pulse Width
µs
Vertical Sync Out (Pin 3)
(a) Pulse Width
Serrations during vertical interval
No serrations during the vertical interval
Modified RSET
197.7
48
197.7
197.7
82
µs
µs
(b) Default Starting Time
Horizontal Scan Rate
Logic Outputs
65
-
15
130
kHz
(a) V
IOH = 40 µA
IOH = 1.6 mA
IOL = -1.6 mA
VCC = 5 V
VCC = 12 V
VCC = 5 V
VCC = 12 V
4.2
11.2
2.4
9.4
-
4.6
11.6
3.4
-
V
V
V
V
V
OH
-
-
10.4
0.3
-
(b) V
0.6
OL
Note 1: When placing the R
resistor and the 0.1µF decoupling capacitor careful attention should be made to ensure that they are as close
SET
as possible to pin 6. Care should also be taken to avoid parasitic capacitive coupling from any output pin (pins 1, 3, 5 and 7) to pin 6.
Note 2: Measured from slicing point of input falling edge to 50% point of composite sync falling edge.
ORDERING INFORMATION
Part Number
GS1881 - CDA
GS1881 - CKA
GS1881 - CTA
GS1881 - IDA
GS1881 - IKA
GS1881 - ITA
Package Type
8 PDIP
Temperature Range
0° to 70° C
8 SOIC
0° to 70° C
8 TAPE
0° to 70° C
8 PDIP
-25° to 85° C
-25° to 85° C
-25° to 85° C
CAUTION
ELECTROSTATIC
SENSITIVE DEVICES
8 SOIC
8 TAPE
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
520 - 23 - 03
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