1. Pin Out
1.1 Pin Assignment
1
2
3
4
5
6
7
8
9
10
VCO_
VDD
LB_CONT
VBG
LF
STAT0
STAT1 IO_VDD PCLK DOUT18 DOUT17
A
B
C
PLL_
VDD
VCO_
GND
A_VDD
SDI
RSV
STAT2 STAT3 IO_GND DOUT19 DOUT16 DOUT15
RESET
PLL_
VDD
PLL_
VDD
A_GND
STAT4 STAT5
DOUT12 DOUT14 DOUT13
_TRST
PLL_
GND
CORE
_GND _VDD
CORE
JTAG/
SDI
A_GND A_GND
SW_EN
IO_GND IO_VDD
HOST
D
E
PLL_
GND
CORE
_GND _VDD
CORE SDOUT_ SDIN_
EQ_VDD EQ_GND A_GND
DOUT10 DOUT11
DOUT8 DOUT9
TDO
TDI
PLL_
GND
CORE
_GND _VDD
CORE
CS_
TMS
SCLK_
TCK
AGCP
RSV
A_GND
F
CORE
_GND
CORE SMPTE_
_VDD BYPASS
CORE
_GND
AGCN A_GND RC_BYP
DVB_ASI IO_GND IO_VDD
G
CORE
_GND
20bit/
10bit
BUFF_ BUFF_
XTAL_
OUT
IOPROC_
TIM_861
RSV
DOUT6 DOUT7
EN/DIS
RSV
RSV
RSV
H
J
VDD
GND
SDO_
EN/DIS
SDO
RSV
RSV
XTAL2 IO_GND DOUT1 DOUT4 DOUT5
XTAL1 IO_VDD DOUT0 DOUT2 DOUT3
STANDBY
RSV
SDO
K
1.2 Pin Descriptions
Table 1-1: Pin Descriptions
Pin
Name
Timing
Type
Description
Number
A1
A2
A3
A4
VBG
LF
Analog Input
Analog Input
Analog Input
Input Power
Band Gap voltage filter connection.
Loop Filter component connection.
LB_CONT
VCO_VDD
Connection for loop bandwidth control resistor.
POWER pin for the VCO. Connect to 1.2V DC analog through an RC
filter (see 5. Application Reference Design). VCO_VDD is nominally
0.7V. (Do not connect directly to 0.7V).
GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated
Adaptive Cable Equalizer
8 of 104
Data Sheet
48004 - 2
November 2009
GENNUM [ GENNUM CORPORATION ]
