APPLICATION NOTES
(1) Choosing the Appropriate Input Coupling Capacitor to
Optimize Slicing Level and Hum Rejection
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127
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Thevideodesignercanadjusttheslicinglevelbychoosingthe
valueoftheinputcouplingcapacitor.Therelationshipbetween
slicing level and input coupling capacitor is described by the
following equation.
IDIS
∆VSLICE
=
∆T = VDROOP
87
CC
77
0.01 0.02 0.03 0.04 0.05 0.06 0.07
0.08 0.09 0.10
where:
IDIS = clamp discharge current = 11 µA
∆T = TLINE - TSYNC = (63.5 µs - 4.7 µs)
CC = input coupling capacitor
INPUT COUPLING CAPACITOR (µF)
Fig. 21 Slicing Level vs Input Coupling Capacitor
Figure 21 is a graphical representation of this equation and
photographs 1 and 2 show the input video waveforms
for 0.1 µF and 0.01 µF input capacitors respectively. The
advantage in choosing a smaller input coupling capacitor, is
increased hum rejection as the following analyses illustrates.
CH1
CH2
CH2
CH1
8
VIDEO
2
4
0.1µF
75Ω
6
680k
0.1µ
Test Circuit 1
Photograph 1
CH1
CH2
CH2
CH1
8
6
VIDEO
2
0.01µF
75Ω
4
680k
0.1µ
Test Circuit 2
Photograph 2
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