Table 1-1: Pin Descriptions (Continued)
Pin
Number
11
Name
Timing
Type
Description
SD/HD
Non
Synchronous
Input /
Output
CONTROL SIGNAL
INPUT /
STATUS SIGNAL
OUTPUT
Signal
levels are LVCMOS/LVTTL
compatible.
This pin will
be
an input set
by
the application layer in slave mode, and
will
be
an output set
by
the
device
in master mode.
Master Mode (MASTER/SLAVE = HIGH)
The
SD/HD
signal will
be
LOW whenever the received serial
digital
signal is 1.485Gb/s or 1.485/1.001Gb/s.
The
SD/HD
signal will
be
HIGH whenever the received serial
digital
signal is 270Mb/s.
Slave
Mode (MASTER/SLAVE = LOW)
When set LOW, the
device
will
be configured
for the reception of
1.485Gb/s or 1.485/1.001Gb/s signals only and will not lock to any
other serial
digital
signal.
When set HIGH, the
device
will
be configured
for the reception of
270Mb/s signals only and will not lock to any other serial
digital
signal.
NOTE: When in slave mode, reset the
device
after the
SD/HD
input has
been
initially
configured,
and after each subsequent
SD/HD data
rate
change.
NOTE: This pin has an internal pull-up resistor of 100K.
12
20bit/10bit
Non
Synchronous
Input
CONTROL SIGNAL
INPUT
Signal
levels are LVCMOS/LVTTL
compatible.
Used to select the output
data bus
width in
SMPTE
or Data-Through
modes. This signal is ignored in DVB-ASI mode.
When set HIGH, the parallel output will
be
20-bit
demultiplexed data.
When set LOW, the parallel outputs will
be
10-bit multiplexed
data.
13
IOPROC_EN/DIS
Non
Synchronous
Input
CONTROL SIGNAL
INPUT
Signal
levels are LVCMOS/LVTTL
compatible.
Used to enable or
disable
I/O processing features.
When set HIGH, the following I/O processing features of the
device
are
enabled:
• EDH
CRC
Error
Correction
(SD-only)
• ANC Data
Checksum Correction
• Line-based
CRC
Error
Correction
(HD-only)
• Line Number Error
Correction
(HD-only)
• TRS Error
Correction
• Illegal
Code
Remapping
To enable a subset of these features, keep IOPROC_EN/DIS HIGH and
disable
the individual feature(s) in the IOPROC_DISABLE register
accessible via the host interface.
When set LOW, the I/O processing features of the
device
are
disabled,
regardless of whether the features are enabled in the
IOPROC_DISABLE register.
GS1560A/GS1561 HD-LINX® II Dual-Rate Deserializer
Data Sheet
27360 - 12
June 2009
9 of 79
GENNUM [ GENNUM CORPORATION ]
