Alternatively, if the test capabilities are to be used in the system, the host may still
control the JTAG/HOST input signal, but some means for tri-stating the host must exist
in order to use the interface at ATE. This is represented in Figure 4-15.
Application HOST
GS1560A / GS1561
CS_TMS
SCLK_TCK
SDIN_TDI
SDOUT_TDO
JTAG_HOST
Tri-State
In-circuit ATE probe
Figure 4-15: System JTAG
Please contact your Gennum representative to obtain the BSDL model for the
GS1560A/GS1561.
4.14 Device Power Up
The GS1560A/GS1561 has a recommended power supply sequence. To ensure correct
power up, power the CORE_VDD pins before the IO_VDD pins.
Device pins may also be driven prior to power up without causing damage.
To ensure that all internal registers are cleared upon power-up, the application layer
must hold the RESET_TRST signal LOW for a minimum of 1ms after the core power
supply has reached the minimum level specified in Table 2-1. See Figure 4-16.
4.15 Device Reset
In order to initialize all internal operating conditions to their default states the
application layer must hold the RESET_TRST signal LOW for a minimum of treset = 1ms.
When held in reset, all device outputs will be driven to a high-impedance state.
+1.8V
+1.65V
CORE_VDD
treset
treset
RESET_TRST
Reset
Reset
Figure 4-16: Reset Pulse
GS1560A/GS1561 HD-LINX® II Dual-Rate Deserializer
Data Sheet
70 of 79
27360 - 12
June 2009
GENNUM [ GENNUM CORPORATION ]
