PIN DESCRIPTIONS (Continued)
NUMBER
32, 33
SYMBOL
LEVEL
TYPE
DESCRIPTION
SP_VEE
Power
Input
Negative Supply. Most negative power supply connection for the
parallel output stage.
34
PCLK_OUT
TTL
Output
Output Clock. The device uses PCLK_OUT for clocking the output
data stream from DATA_OUT[19:0]. This clock is also used to clock
the data into the GS1500 HDTV Deformatter or GS1510 Deformatter.
35
36
PCLK_VCC
PCLK_VEE
Power
Power
TTL
Input
Input
Positive Supply. Most positive supply connection for parallel clock
output stage.
Negative Supply. Most negative power supply connection for parallel
clock output stage.
41, 42, 43, 44,
45, 46, 47, 48,
49, 50, 53, 54,
55, 56, 59, 60,
61, 62, 63, 64
DATA_OUT[19:0]
Output
Parallel Data Output Bus. The device outputs a 20 bit parallel data
stream running at 74.25 or 74.25/1.001MHz on DATA_OUT[19:0].
DATA_OUT[19] is the MSB and DATA_OUT[0] is the LSB.
72
73
74
LFA_VCC
LFA
Power
Analog
Analog
Input
Output
Input
Positive Supply. Loop filter most positive power supply connection.
Control Signal Output. Control voltage for GO1515 VCO.
LBCONT
Control Signal Input. Used to provide electronic control of Loop
Bandwidth.
75
76
LFA_VEE
DFT_VEE
Power
Power
Input
Input
Negative Supply. Loop filter most negative power supply connection.
Most negative power supply connection - enables the jitter
demodulator functionality. This pin should be connected to ground. If
left floating, the DM function is disabled resulting in a current saving of
340µA.
79, 80
DM, DM
Analog
Output
Test Signal. Used for manufacturing test only.
These pins must be floating for normal operation.
81, 85
86
LFS, LFS
IJI
Analog
Analog
Input
Loop Filter Connections.
Output
Status Signal Output. Approximates the amount of excessive jitter on
the incoming DDI and DDI input.
89
91
VCO
VCO
Analog
Analog
Input
Input
Control Signal Input. Input pin is AC coupled to ground using a 50Ω
transmission line.
Control Signal Input. Voltage controlled oscillator input. This pin is
connected to the output pin of the GO1515 VCO.
This pin must be connected to the GO1515 VCO output pin via a 50Ω
transmission line.
93, 96
98
PLCAP, PLCAP
PLL_LOCK
Analog
TTL
Input
Control Signal Input. Phase lock detect time constant capacitor.
Output
Status Indicator Signal. This signal is a combination (logical AND) of
the carrier detect and phase lock signals.
When input is present and PLL is locked, the PLL_LOCK goes high
and the outputs are valid. When the PLL_LOCK output is low the data
output is muted (latched at the last state).
PLL_LOCK is independent of the BYPASS signal.
105
BYPASS
TTL
Input
Control Signal Input. Selectable input that controls whether the input
signal is reclocked or passed through the chip.
When BYPASS is high; the input signal is reclocked.
When BYPASS is low; the input signal is passed through the chip and
not reclocked. Muting does not effect bypassed signal.
8 of 19
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