PIN DESCRIPTIONS
NUMBER
1, 2, 3, 4, 6, 5,
7, 8, 9, 10, 11,
12, 13, 14, 15,
16, 22, 23, 24,
25, 26, 27, 28,
29, 37, 38, 39,
40, 51, 52, 57,
58, 65, 66, 67,
68, 69, 70, 71,
77, 78, 82, 83,
84, 87, 88, 90,
92, 94, 95, 97,
99, 100, 101,
102, 103, 104,
107, 111, 114,
115, 116, 117,
118, 119, 120,
121, 122, 123,
124, 125, 126,
127, 128
17, 18
SYMBOL
NC
LEVEL
TYPE
DESCRIPTION
No Connect.
Leave these pins floating.
GS1540
DDO, DDO
ECL/PECL
compatible
Output
Digital Data Output.
Differential serial outputs. 50Ω pull up resistors are
included on chip. Note that these outputs are not cable drivers.
Ensure that the trace length between the GS1540 and the GS1508
Cable driver is kept to a minimum and that a PCB trace characteristic
impedance of 50Ω is maintained between the GS1508 and the
GS1540. 50Ω end termination is recommended.
19
DDO_V
EE
DDO_EN
Power
Input
Negative Supply.
Most negative power supply connection for serial
data output stage.
Control Signal Input.
Used to enable or disable the serial output stage.
If a loop through function is not required, then this pin should be tied
to the most positive power supply voltage.
When DDO_EN is tied to the most negative power supply voltage, the
DDO, DDO outputs are enabled.
When DDO_EN is tied to the most positive power supply voltage, the
DDO, DDO outputs are disabled.
20
Power
Input
21
DDO_V
CC
SP_V
CC
SP_V
EE
PCLK_OUT
Power
Input
Positive Supply.
Most positive power supply connection for serial data
output stage.
Positive Supply.
Most positive power supply connection for serial to
parallel converter stage.
Negative Supply.
Most negative power supply connection for the
parallel output stage.
Output Clock.
The device uses PCLK_OUT for clocking the output
data stream from DATA_OUT[19:0]. This clock is also used to clock
the data into the GS1500 HDTV Deformatter, or GS1510 HDTV
Deformatter.
Positive Supply.
Most positive supply connection for parallel clock
output stage.
Negative Supply.
Most negative power supply connection for parallel
clock output stage.
Parallel Data Output Bus.
The device outputs a 20 bit parallel data
stream running at 74.25 or 74.25/1.001MHz on DATA_OUT[19:0].
DATA_OUT[19] is the MSB and DATA_OUT[0] is the LSB.
30, 31
Power
Input
32, 33
Power
Input
34
TTL
Output
35
PCLK_V
CC
PCLK_V
EE
DATA_OUT[19:0]
Power
Input
36
Power
Input
41, 42, 43, 44,
45, 46, 47, 48,
49, 50, 53, 54,
55, 56, 59, 60,
61, 62, 63, 64
TTL
Output
7 of 17
GENNUM CORPORATION
522 - 27 - 03
GENNUM [ GENNUM CORPORATION ]
