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GS1532-CFE3 参数 Datasheet PDF下载

GS1532-CFE3图片预览
型号: GS1532-CFE3
PDF下载: 下载PDF文件 查看货源
内容描述: GS1532 HD- LINX -TM II多速率串行器 [GS1532 HD-LINX-TM II Multi-Rate Serializer]
分类和应用: 消费电路商用集成电路
文件页数/大小: 52 页 / 866 K
品牌: GENNUM [ GENNUM CORPORATION ]
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GS1532 Data Sheet  
3. Detailed Description  
3.1 Functional Overview  
The GS1532 is a multi-rate serializer with an integrated cable driver. When used in  
conjunction with the external GO1525 Voltage Controlled Oscillator, a transmit  
solution at 1.485Gb/s, 1.485/1.001Gb/s or 270Mb/s is realized.  
The device has three different modes of operation which must be set by the  
application layer through external device pins.  
When SMPTE mode is enabled, the device will accept 10-bit multiplexed or 20-bit  
demultiplexed SMPTE compliant data at both HD and SD signal rates. The  
device’s additional processing features are also enabled in this mode.  
In DVB-ASI mode, the GS1532 will accept an 8-bit parallel DVB-ASI compliant  
transport stream on its upper input bus. The serial output data stream will be  
8b/10b encoded and stuffed.  
The GS1532’s third mode allows for the serializing of data not conforming to  
SMPTE or DVB-ASI streams.  
The provided serial digital outputs feature a high impedance mode, output mute on  
loss of parallel clock and adjustable signal swing. The output slew rate is  
automatically controlled by the SD/HD setting.  
In the digital signal processing core, several data processing functions are  
implemented including SMPTE 352M and EDH data packet generation and  
insertion, and automatic video standards detection. These features are all enabled  
by default, but may be individually disabled via internal registers accessible  
through the GSPI host interface.  
Finally, the GS1532 contains a JTAG interface for boundary scan test  
implementations.  
3.2 Parallel Data Inputs  
Data inputs enter the device on the rising edge of PCLK as shown in Figure 3-1.  
The input data format is defined by the setting of the external SD/HD,  
SMPTE_BYPASS and DVB_ASI pins and may be presented in 10-bit or 20-bit  
format. The input data bus width is controlled independently from the internal data  
bus width by the 20bit/10bit input pin.  
21498 - 6 June 2005  
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