25.72kHzUI,
the
synchronous
lock
time
is
should be no less than 5.6µF. This would result in 340ms of
lock time. If necessary, extra margin can be built by
increasing these capacitors at the expense of a longer
asynchronous lock time.
0.3535/25.72k=13.75µs. Since the CCP1, CCP2 and CCP3 are
also charged, it is measured to be about 11µs which is
slightly less than the calculated value of 13.75µs.
Bandwidths lower than 129kHz at 0.2UI modulation have
not been characterized, but it is believed that the
The Kƒ of the VCO (GO1515) is specified with a minimum of
11MHz/V and maximum of 21MHz/V which is about 32%
variation. The 500 x ΙP/2 will vary about 10%. The resulting
bandwidth factor would approximately vary by 45% when
no RCP1 and CCP3 are used. ΙP by itself may vary by 30% so
the variability for lower bandwidths will increase by an
additional 30%.
bandwidth could be further lowered. Since
a lower
bandwidth has less correction for noise, extra care should
be taken to minimize board noise. Figures 18 and 19 show
the two measured loop bandwidths at these two settings.
Table 2 summarizes the two bandwidth settings.
The CCP1 and CCP2 capacitors should be changed with
reduced bandwidths. Smaller CCP1 and CCP2 capacitors
would result in jitter peaking, lower stability, less probability
of locking but at the same time lowering the asynchronous
lock time. Therefore, there is
a
trade-off between
asynchronous lock time and jitter peaking/stability. These
capacitors should be as large as possible for the allowable
lock time and should be no smaller than the allowed value.
With the recommended values, jitter peaking of less than
0.1dB has been measured at the lower loop bandwidth as
shown in Figure 17. At higher loop bandwidths, it is difficult
to measure jitter peaking because of the limitation of the
measurement unit.
Fig. 18 Typical Jitter Transfer Curve at Setting A in Table 2
Fig. 17 Typical Jitter Peaking
However, because relatively larger CCP1 and CCP2
capacitors can be used, over-damping of the loop response
occurs. An accurate jitter peaking measurement of 0.1dB
for the GS1522 requires the modulation source to have a
constant amount of jitter modulation index (within 0.1dB or
1.2%) over the frequency range beyond the loop
bandwidth.
Fig. 19 Typical Jitter Transfer Curve at Setting B in Table 2
It has been determined that for 282.9kHzUI, the minimum
value of the CCP1 and CCP2 capacitors should be no less
than 0.5µF. For added margin, 1µF capacitors are
recommended. The 1µF value gives a lock time of about
60ms in one attempt. For 25.72kHzUI, these capacitors
12
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