PIN DESCRIPTIONS
NUMBER
1, 95
SYMBOL
V
EE3
PCLK_IN
NC
LEVEL
Power
TYPE
Input
DESCRIPTION
Negative Supply.
Most negative power supply connection, for input
stage.
Parallel Data Clock.
74.25 or 74.25/1.001MHz
No Connect.
These pins are not used internally. These pins should
be floating.
2
3, 4, 5, 6, 7, 8,
9, 11, 12, 14,
19, 20, 32, 33,
34, 35, 36, 37,
38, 39, 40, 41,
42, 43,46, 50,
51, 52, 56, 60,
61, 62, 65, 66,
67, 68, 69, 70,
71, 72, 73, 80,
81, 83, 93, 97,
98, 99, 100,
101, 102, 108,
109, 116, 117,
120, 121
10
TTL
Input
GS1522
BUF_V
EE
Power
TEST
Negative Supply/Test Pin.
Most negative power supply connection.
For buffer for oscillator/divider for test purposes only. Leave
floating for normal operation.
Test Pin.
Test block output. Leave floating for normal operation.
Status Signal Output.
Indicates when the GS1522 is phase locked
to the incoming PCLK_IN clock signal. LOGIC HIGH indicates PLL
is in Lock. LOGIC LOW indicates PLL is out of Lock.
Control Signal Input.
Used to bypass the scrambling function if
data is already scrambled by GS1501 or if non-SMPTE encoded
data stream such as 8b/10b is to be transmitted. When BYPASS is
LOW, the SMPTE scrambler and NRZ(I) encoder are enabled.
When BYPASS is HIGH, the SMPTE scrambler and NRZ(I) encoder
are bypassed.
Control Signal Input.
Used to reset the SMPTE scrambler. For logic
HIGH; Resets the SMPTE scrambler and NRZ(I) encoder. For logic
LOW: normal SMPTE scrambler and NRZ(I) encoder operation.
Negative Supply.
Most negative power supply connection. For
Cable Driver outputs and all other digital circuitry excluding input
stage and PLL stage.
Positive Supply.
Most positive power supply connection. For Cable
Driver outputs and all other digital circuitry excluding input stage
and PLL stage.
Control Signal Input.
Used to enable or disable the second serial
data output stage. This signal must be tied to GND to enable this
stage. Do not connect to a logic LOW.
Control Signal Input.
External resistor is used to set the data output
amplitude for SDO1 and SDO1. Use a ±1% resistor.
Serial Data Output Signal.
Current mode serial data output #1.
Use 75Ω ±1% pull up resistors to V
CC2
.
13
15
XDIV20
PLL_LOCK
TTL
TTL
TEST
Output
16
BYPASS
TTL
Input
17
RESET
TTL
Input
18, 26, 27, 28,
29, 30, 59
V
EE2
Power
Input
21, 22, 23, 24,
25, 45, 57
V
CC2
Power
Input
31
SDO1_EN
Power
Input
44
R
SET1
SDO1, SDO1
Analog
Input
47, 49
Output
48, 54
53, 55
SDO_NC
SDO0, SDO0
Analog
Output
No Connect.
Not used internally. This pin must be left floating.
Serial Data Output Signal.
Current mode serial data output #0. Use
75Ω ± 1% pull up resistors to V
CC2
.
Control Signal Input.
External resistor is used to set the data output
amplitude for SDO0 and SDO0. Use a ±1% resistor.
58
R
SET0
Analog
Input
5 of 20
GENNUM CORPORATION
522 - 26 - 03
GENNUM [ GENNUM CORPORATION ]
