DETAILED DESCRIPTION
The GS1515 is a single standard re-timer for serial digital
HDTV signals at 1.485Gb/s and 1.485/1.001Gb/s.
Lastly, because most of the PLL circuitry is digital, it is very
robust similar to any other digital systems which are
generally more robust than their analog counterparts.
Additionally signals like DM/DM which represent the internal
functionality can be generated without adding additional
artifacts. Thus, system debugging is also possible with
these features. The complete slew PLL is made up of
several blocks including the phase detector, the charge
pump and an external Voltage Controlled Oscillator (VCO).
For the device descriptions, reference should be made to
the Functional Block Diagram on the cover page of the data
sheet.
UNIQUE SLEW PHASE LOCK LOOP (S-PLL):
A unique feature of the GS1515 is the innovative slew phase
lock loop (S-PLL). When a step phase change is applied to
the PLL, the output phase gains constant rate of change
with respect to time. This behavior is termed slew. Figure 13
shows an example of input and output phase variation over
time for slew and linear (conventional) PLLs. Since the
slewing is a non-linear behavior, the small signal analysis
cannot be done in the same way as it is done for the
standard PLL. However, it is still possible to plot input jitter
transfer characteristics at a constant input jitter modulation.
INPUT BUFFER
The input buffer is a self-biased circuit. On-chip 50Ω
termination resistors provide a seamless interface for other
HD-LINX™ products such as the GS1504 Adaptive Cable
Equalizer.
0.2
INPUT
PHASE DETECTOR
0.1
0.0
OUTPUT
The phase detector portion of the slew PLL used in GS1515
is a bi-level digital phase detector. It indicates whether the
data transition occurred before or after with respect to the
falling edge of the internal clock. When the phase detector
is locked, the data transition edges are aligned to the falling
edge of the clock. The input data is then sampled by the
rising edge of the clock, as shown in Figure 14. In this
manner, the allowed input jitter is 1UI p-p in an ideal
situation. However, due to setup and hold time, the GS1515
typically achieves 0.8UI p-p input jitter tolerance without
causing any errors in this block. When the signal is locked
to the internal clock, the control output from the phase
detector is refreshed at the transition of each rising edge of
the data input. During this time, the phase of the clock drifts
in one direction.
SLEW PLL RESPONSE
0.2
0.1
0.0
INPUT
OUTPUT
LINEAR (CONVENTIONAL) PLL RESPONSE
Fig. 13 PLL Characteristics
PHASE ALIGNMENT
EDGE
RE-TIMING
EDGE
Slew PLLs offer several advantages such as excellent noise
immunity. Because of the infinite bandwidth for an infinitely
small input jitter modulation (or jitter introduced by VCO),
the loop corrects for that immediately thus the small signal
noise of the VCO is cancelled. The GS1515 uses an
extremely clean, external VCO called the GO1515
(reference should be made to the GO1515 Data Sheet). In
addition, the bi-state digital phase detector provides
constant loop bandwidth that is independent of the data
transition density. The loop bandwidth of a conventional tri-
stable charge pump drops with reducing data transitions.
During pathological signals, the data transition density
reduces from 0.5 to 0.05, but the slew PLL’s performance
does not change.
IN-PHASE CLOCK
0.8UI
INPUT DATA
WITH JITTER
OUTPUT DATA
Fig. 14 Phase Detector Characteristics
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