GF9330 Data Sheet
Table 1-1: Pin Descriptions (Continued)
Symbol
HOST_EN
Pin Grid
E4
Type
I
Description
Host interface enable. When set HIGH, the GF9330 will be configured through
the host interface. On a high to low transition of HOST_EN the GF9330 will
replace all register settings in the host interface with the values present on the
external pins of the device including: STD[4:0], MODE[2:0], FVH_EN, FF_EN
and XVOCLK_SL.
Host interface mode selection. Enables serial mode operation when HIGH.
Enables parallel mode operation when LOW.
Functions as an active low chip select input for host interface parallel mode
operation. Functions as a serial clock input for host interface serial mode
operation.
Host interface bi-directional data bus for parallel mode. In serial mode, DAT[7]
serves as the serial data output pin and DAT[0] serves as the serial data input
pin.
Host interface Read/Write control for parallel mode. A read cycle is defined
when HIGH, a write cycle is defined when LOW.
Host interface Address/Data control for parallel mode. The data bus contains
an address when HIGH, a data word when LOW. In serial mode, this pin
serves as the chip select (active low).
Video output clock. Output frequency based on selected output standard. See
Output data bus for separate luminance or multiplexed luminance and colour
difference video data. See
Output data bus for luminance video data during dual pixel mode operation.
See
Output data bus for colour difference video data.
See
SER_MD
CS
G1
P2
I
I
DAT_IO[7:0]
R4, R3, R2, R1, T4, T3,
T2, T1
P3
P1
I/O
R_W
A_D
I
I
VCLK_OUT
Y1_OUT[11:0]
A20
D18, E20, E19, E18, F20,
F19, F18, F17, G20, G19,
G18, G17
H20, H19, H18, H17, J20,
J19, J18, J17, K20, K19,
K18, L18
L19, L20, M17, M18, M19,
M20, N17, N18, N19, N20,
P17, P18
P19, P20, R17, R18, R19,
R20, T18, T19, T20, U18,
U19, U20
B20
O
O
Y2_OUT[11:0]
O
C1_OUT[11:0]
O
C2_OUT[11:0]
O
Output data bus for colour difference video data during dual pixel mode
operation. See
Control signal output. When the GF9330’s internal algorithm detects a 3:2
sequence in the video stream the LOCK_32 signal is set HIGH. Otherwise,
LOCK_32 is LOW.
Control signal input/output. For external 3:2 sequence detection, the
XSEQ[3:0] pins will be used to provide the 3:2 sequence information. For
internal 3:2 detection the XSEQ[3:0] pins output the detected 3:2 sequence
information. See
Output control signal. H_OUT is HIGH during horizontal blanking.
Output control signal. F_OUT is LOW during field 1 and HIGH during field 2.
Output control signal. V_OUT is HIGH during vertical blanking.
SDRAM bank 1 clock.
Active low SDRAM chip select for Field Buffer 1.
LOCK_32
O
XSEQ[3:0]
D19, D20, C19, C20
I/O
H_OUT
F_OUT
V_OUT
S1_CLK
S1_CS
V20
V19
W20
Y10
Y3
O
O
O
O
O
Proprietary and Confidential
18283 - 4
June 2004
5 of 42
GENNUM [ GENNUM CORPORATION ]
