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GF9320 参数 Datasheet PDF下载

GF9320图片预览
型号: GF9320
PDF下载: 下载PDF文件 查看货源
内容描述: 扩展处理器 [Scaling Processor]
分类和应用:
文件页数/大小: 60 页 / 909 K
品牌: GENNUM [ GENNUM CORPORATION ]
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GF9320 Data Sheet  
Table 1-1: Pin Descriptions  
Symbol  
Pin Grid  
Type  
Description  
YIN[9:0]  
H1, J4, J3, J2, J1, K2, K1,  
L4, L3, L2  
I
10-bit multiplexed signed luminance / signed offset colour difference data  
input.  
Note that either input must include TRS words.  
CIN[9:0]  
CK_IN  
L1, M4, M3, M2, M1, N4,  
N3, N2, N1, P1  
I
I
10-bit signed offset colour difference data input.  
Note that theinput must include TRS words.  
G2  
Input clock.  
Note that it is equal Y data rate for separate Y and C inputs, and is equal to 2x  
Y data rate for multiplexed YC input.  
CK_V  
G25  
I
Vertical processing clock.  
Note that it is usually the higher of CK_IN or CK_OUT.  
CK_OUT  
FILM_FR  
AA26  
H2  
I
I
Output clock.  
Input film sequence reset.  
Output frame reset.  
OUT_FRST  
GOUT[9:0]  
E1  
I
K25, K26, L23, L24, L25,  
L26, M23, M25, M26, N25  
O
10 / 8-bit unsigned green data output OR  
10 / 8-bit unsigned luminance data output OR  
10 / 8-bit multiplexed signed luminance / signed offset colour difference data  
output.  
BOUT[9:0]  
ROUT[9:0]  
P26, P25, P24, P23, R26,  
R23, T26, T25, T24, T23  
O
O
10 / 8-bit unsigned blue data output OR  
10 / 8-bit signed offset (B-Y) data output OR  
10/8-bit multiplexed signed offset colour difference data output.  
U26, U25, V25, V24, V23,  
W26, W25, W24, W23,  
Y26  
10 / 8-bit unsigned red data output OR  
10 / 8-bit signed offset (R-Y) data output.  
OUT_CK  
OUT_F  
J26  
T3  
O
O
Output clock timed to clock output data.  
Output format frame / field signal.  
Note that the output is 3 clocks in advance of output video data.  
OUT_V  
OUT_H  
T2  
T1  
O
O
Output format vertical signal.  
Note that the output is 3 clocks in advance of output video data.  
Output format horizontal signal.  
Note that the output is 3 clocks in advance of output video data.  
SIF_OUT  
SIF_IN  
V4  
V1  
V2  
V3  
F1  
O
Serial interface control data out.  
Serial interface control data in.  
Serial interface clock.  
I
SIF_CK  
I
SIF_RST  
RST  
I
I
Serial interface reset.  
Power-on reset.  
DATA_A[19:0]  
A15, D14, C14, B14, A14,  
A13, B13, A12, B12, C12,  
D12, C11, D11, A10, B10,  
A9, B9, C9, D9, A8  
I/O  
Data bus for memory array A.  
Proprietary and Confidential 18090 - 7  
November 2004  
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