GL9711 PCI Express
TM
PIPE x1 PHY
CHAPTER 2
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FEATURES
Complies with PCI Express Base Specification rev. 1.0a
Complies with Intel’s PHY Interface for PCI Express Architecture rev. 1.0
Integrates 2.5 gigabit per second (Gpbs) Serializer/Deserializer
Supports 8-bit or 10-bit parallel interface @250MHz
Supports 16-bit parallel interface @125MHz
Supports DDR configuration for 8-bit or 10-bit mode
Beacon transmission and reception
Receiver detection
Transmission and detection of electrical idle
Clock tolerance for 600 ppm in frequencies between bit rates at the two end of a Link
On-chip 8-bit/10-bit encoding/decoding and comma alignment
On-chip PLL provides clock synthesis
1.8-V power supply for core
2.5-V power supply for IO
Above 2.0 kV ESD protection
0.18
µm
process
Available in LFBGA-233 package
©2000-2006
Genesys Logic Inc. - All rights reserved.
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