GL9701 PCI ExpressTM to PCI Bridge
CHAPTER 2 FEATURES
2.1 PCI Express Features
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Compliant to PCI Express Base Specification Revision 1.0a
Compliant to PCI Express to PCI Bridge Specification Revision 1.0
Support Single One-Lane PCI Express Connection
Support 32-bit CRC Covering All Transmitted Data Packets
Support 16-bit CRC On All Link Message Information
Support PCI Express Advanced Error Reporting Capability
Support Error Forwarding Including Data Poisoning and PCI Bus Parity Errors.
Support 100MHz PCI Express Differential Reference Clock.
Secondary Side Initialization via Type 0 Configuration Cycles
Support Variable Payload Size (up to 512 bytes)
Support Variable Size of Read Request (up to 512 bytes)
2.2 PCI Interface Features
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Compliant to PCI Local Bus Specification Revision 3.0
Support PCI 32-bit, 33/66 MHz, 3.3V, NOT 5V tolerant
Support Five External REQ/GNT Pairs For Internal Arbiter
Support PCI LOCK Operation
Support up to Two PCI Delayed Transaction (memory read, I/O read/write, and configuration read/write)
Support Clock Run Operation
Support Five 33MHz/66MHz PCI Clock Outputs
2.3 Power Management
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Support D0, D1, D2, D3hot and D3cold device power states defined in PCI Power Management
Specification Rev 1.1
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Support PME event propagation on behalf of PCI devices
Side-band WAKE# signals
PCI Express Active Power Management states (ASPM) : L0s and L1
Support link power management: L0, L0s, L1, L2
In-band beacon generation
Integrated AUX Power Plane
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