GL811E USB 2.0 to ATA/ATAPI Bridge Controller
6.4 AC Characteristics- ATA/ ATAPI
The GL811E complies with ATA / ATAPI-6 specification rev 1.0, which supports following data transfer modes:
1. DMA (Direct Memory Access) data transfer:
DMA data transfer means of data transfer between device and host memory without host processor
intervention.
- Multiword DMA: Multiword DMA is a data transfer protocol used with the READ DMA, WRITE
DMA, READ DMA QUEUED, WRITE DMA QUEUED and PACKET commands. When a
Multiword DMA transfer is enabled as indicated by IDENTIFY DEVICE or IDENTIFY PACKET
DEVICE data, this data transfer protocol shall be used for the data transfers associated with these
commends. (Please refer to the ATA / ATAPI-6 specification rev 1.0 for more information.)
- Ultra DMA: Ultra DMA Is a data transfer protocol used with the READ DMA, WRITE DMA,
READ DMA QUEUED, WRITE DMA QUEUED and PACKET commands. When this protocol is
enabled, the Ultra DMA protocol shall be used instead of the Multiword DMA protocol when these
commands are issued by the host. This protocol applies to the Ultra DMA data burst only. (Please
refer to the ATA / ATAPI-6 specification rev 1.0 for more information.)
Following listed the symbols and their respective definitions that are used in the timing diagram:
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-
-
-
-
-
-
Signal transition (asserted or negated)
Data transition (asserted or negated)
Data valid
Undefined but not necessarily released
Asserted, negated or released
Released
The “other” condition if a signal is shown with no change
All signals are shown with the asserted condition facing to the top of the page. The negated condition is shown
towards the bottom of the page relative to the asserted condition.
The interface uses a mixture of negative and positive signals for control and data. The terms asserted and
negated are used for consistency and are independent of electrical characteristics.
In all timing diagrams, the lower line indicates negated, and the upper line indicates asserted. The following
illustrates the representation of a signal named Test going from negated to asserted and back to negated, based
on the polarity of the signal.
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