GL811E USB 2.0 to ATA/ATAPI Bridge Controller
CHAPTER 4 BLOCK DIAGRAM
DMACK_
DIOR_
DIOW_
CS1_,
CS0_
DA2
DA1
DA0
CLK15
GPIO1
GPIO7
CPU
Control Register
RPU
8
CONTROL FIFO
CLK30
RXSTS
TXCTL
DPF
DPH
TXFIFO0
TXFIFO1
RXFIFO0
RXFIFO1
8/16-Bit
IDE
IODD15-0
SIE
UTMI USB2.0
LOGIC TXCVR
INTRQ
CBLID_
DMARQ
IORDY
4
Engine
DMF
DMH
16
12-96MHz
DATA
RREF
X10
X40
Clkgen
12MHz
Figure 4.1 - Block Diagram
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