MB90610A Series
■ BLOCK DIAGRAM
X0, 1
7
CPU
Clock
control circuit
RST
F2MC-16L family core
HST
MD0 to MD2
Interrupt controller
RAM
8/16-bit PPG
(output switching) × 1channel
PPG0
PPG1
Communication prescaler
3
SIN0 to SIN2
SOT0 to SOT2
SCK0 to SCK2
3
3
UART
AVcc
AVRH, AVRL
AVss
2
A/D converter
(8/10-bit)
ATG
AN0 to AN7
8
8
24
16
IRT0 to IRT7
A00 to A23
D00 to D15
ALE
RD
WRL, WRH
HRQ
External interrupts
2
TIT0, TIT1
TOT0, TOT1
2
Reload timer
External bus
Interface
2
8
HAK
RDY
CS0 to CS7
Chip select outputs
CLK
I/O ports
8
8
8
8
6
8
7
7
6
7
P10 P20 P30 P40 P50 P60 P70 P80 P90 PA1
to to to to to to to to to to
P17 P27 P37 P47 P55 P67 P76 P86 P95 PA7
15
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