MB90480/485 Series
• Range of warranted PLL operation
Internal operating clock frequency vs. Power supply voltage
3.6
Range of warranted PLL operation
3.0
2.7
Normal operating range
16
1.5
4
25
Internal clock fCP (MHz)
Notes: • For A/D operating frequency, refer to “5. A/D Converter Electrical Characteristics”
• Only at 1 multiplied PLL, use with more than fCP = 4 MHz.
Base oscillator frequency vs. Internal operating clock frequency
8 × *3
25
24
6 × *3
No multiplied
3 × *1
20
2 × *1,*2
1 × *1
18
16
4 ×
*1,*2
12
9
8
6
4
1.5
3 4 5 6 8 10 12.5 16
20
25
32
40
50
Base oscillator clock FCH (MHz)
*1 : In setting as 1, 2, 3 and 4 multiplied PLL, when the internal clock is used at 20 MHz < fCP ≤ 25 MHz, set
the PLLOS register to “DIV2 bit = 1” and “PLL2 bit = 1”.
[Example]
When using the base oscillator frequency of 24 MHz at 1 multiplied PLL :
CKSCR register : CS1 bit = “0”, CS0 bit = “0” PLLOS register : PLL2 bit = “1”
When using the base oscillator frequency of 6 MHz at 3 multiplied PLL :
CKSCR register : CS1 bit = “1”, CS0 bit = “0” PLLOS register : PLL2 bit = “1”
[Example]
*2 : In setting as 2 and 4 multiplied PLL, when the internal clock is used at 20 MHz < fCP ≤ 25 MHz, the following
setting is also enabled.
2 multiplied PLL : CKSCR register : CS1 bit = “0”, CS0 bit = “0”
PLLOS register : PLL2 bit = “1”
4 multiplied PLL : CKSCR register : CS1 bit = “0”, CS0 bit = “1”
PLLOS register : PLL2 bit = “1”
*3 : When using in setting as 6 and 8 multiplied PLL, set the PLLOS register to “DIV2 bit = 0” and “PLL2 bit = 1”.
[Example]
When using the base oscillator frequency of 4 MHz at 6 multiplied PLL :
CKSCR register : CS1 bit = “1”, CS0 bit = “0” PLLOS register : PLL2 bit = “1”
When using the base oscillator frequency of 3 MHz at 8 multiplied PLL :
CKSCR register : CS1 bit = “1”, CS0 bit = “1” PLLOS register : PLL2 bit = “1”
[Example]
90
FUJITSU [ FUJITSU ]
