MB90480/485 Series
23. Address Match Detection Function
When the address is equal to a value set in the address detection register, the instruction code loaded into the
CPUisreplacedforciblywiththeINT9instructioncode(01H). Asaresult, whentheCPUexecutesasetinstruction,
the INT9 instruction is executed. Processing by the INT#9 interrupt routine allows the program patching function
to be implemented.
Two address detection registers are supported. An interrupt enable bit is prepared for each register. If the value
set in the address detection register matches an address and if the interrupt enable bit is set at “1”, the instruction
code loaded into the CPU is replaced forcibly with the INT9 instruction code.
(1) Register List
• Program address detection register 0 (PADR0)
Address
7
6
5
4
3
2
1
0
Initial value
B
XXXXXXXX
PADR0 (Low order address) : 001FF0H
R/W
7
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
Address
Initial value
PADR0 (Middle order address) : 001FF1H
B
XXXXXXXX
R/W
7
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
Address
Initial value
B
XXXXXXXX
PADR0 (High order address) : 001FF2H
R/W
R/W
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
• Program address detection register 1 (PADR1)
Address
7
6
Initial value
B
XXXXXXXX
PADR1 (Low order address) : 001FF3H
R/W
7
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
Address
Initial value
B
XXXXXXXX
PADR1 (Middle order address) : 001FF4H
R/W
7
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
Address
Initial value
B
XXXXXXXX
PADR1 (High order address) : 001FF5H
R/W
R/W
R/W
R/W
R/W
3
R/W
2
R/W
1
R/W
0
• Program address detection control status register (PACSR)
Address
7
6
5
4
Initial value
B
00000000
RESV RESV RESV RESV AD1E RESV AD0E RESV
R/W R/W R/W R/W R/W R/W R/W R/W
00009EH
R/W : Readable and writable
X
: Undefined
RESV : Reserved bit
82
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