MB90480/485 Series
(2) Block Diagram
Standby control circuit
Low-power consumption mode control register (LPMCR)
Re-
STP SLP SPL RST TMD CG1 CG0
served
Pin
Pin
high-impedance
control circuit
high-impedance
control
Internal reset
generator circuit
RST
pin
Internal reset
CPU intermittent
operating selector
Intermittent cycle selection
CPU clock
control circuit
Stop, sleep signals
Stop signal
Peripheral
CPU clock
Standby control
Interrupt release
circuit
Peripheral clock
clock control
circuit
Machine clock
Oscillator stabilization wait release
Clock generator module
PLL output select register (PLLOS)
Clock
Oscillator
stabiliza-
tion
selector
⎯
⎯
⎯
⎯
⎯
⎯
⎯ PLL2
2
SCLK
wait period
selector
× 4
2
PLL multiplier
circuit
SCM MCM WS1 WS0 SCS MCS CS1 CS0
Sub clock
generator
circuit
Clock select register (CKSCR)
System
clock
generator
circuit
X0A pin
×
1024
× 2
× 2
× 4
× 4
× 4
× 2
pin
X1A
HCLK MCLK
pin
pin
X0
X1
Timebase
timer
To watchdog timer
HCLK : Oscillator clock
MCLK : Main clock
SCLK : Sub clock
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