MB90480/485 Series
■ BLOCK DIAGRAM
X0, X1, RST
CPU
Clock control
F2MC16LX series core
8
X0A, X1A
Circuit
MD2, MD1, MD0
RAM
Interrupt controller
8/16-bit PPG
PPG0, PPG1
PPG2, PPG3
PPG4, PPG5
ROM
µDMAC
8/16-bit
up/down
counter/timer
AIN0, AIN1
BIN0, BIN1
ZIN0, ZIN1
Communication
prescaler
2
EXTC
MT00
MT01
SIN0
SOT0
SCK0
µPG
UART
SIN1, SIN2
SOT1, SOT 2
SCK1, SCK2
Extended I/O serial
interface × 2 channels
CS0, CS1,
CS2, CS3
Chip select
Input/output timer
AVCC
AVRH
AVSS
ADTG
AN0 to AN7
16-bit input capture ×
2 channels
IN0, IN1
A/D converter
( 10-bit )
16-bit output compare
OUT0, OUT1,
OUT2, OUT3,
OUT4, OUT5
×
6 channels
16-bit free-run timer
TIN0
TOT0
16-bit reload timer
PWC0
SCL
SDA
I2C interface
PWC × 3 channels
PWC1
PWC2
8
External interrupt
IRQ0 to IRQ7
I/O port
8
8
8
8
8
8
8
8
8
8
4
P00 P10 P20 P30 P40 P50 P60 P70 P80 P90 PA0
to to to to to to to to to to to
P07 P17 P27 P37 P47 P57 P67 P77 P87 P97 PA3
: Only MB90485 series
P00 to P07 (8 pins) : with an input pull-up resistance setting register.
P10 to P17 (8 pins) : with an input pull-up resistance setting register.
P40 to P47 (8 pins) : with an open drain setting register.
P70 to P77 (8 pins) : with an open drain setting register.
MB90485 series only
• I2C pin P77 and P76 are N-ch open drain pin (without P-ch) . However, MB90V485B uses
the N-ch open drain pin (with P-ch) .
• P20 to P27, P30 to P37, P40 to P47 and P70 to P77 are also used as 3 V/5 V I/F pin.
• As for MB90V485B, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/
µPG/I2C become CMOS input.
Note : In the above diagram, I/O ports share internal function blocks and pins. However, when a
set of pins is used with an internal module, it cannot also be used as an I/O port.
18
FUJITSU [ FUJITSU ]
