MB3773
EXAMPLE 11 : Circuit for Limiting Upper Clock Input Frequency
VCC (5V)
R2
1
2
3
4
8
7
6
5
RESET
RESET
CT
R1=10kΩ
CK
Tr1
GND
C2
• This is an example application to limit upper frequency fH of clock pulses sent from the
microcomputer.
If the CK cycle sent from the microcomputer exceeds fH, the circuit generates a reset
signal.
(The lower freqency has already been set using Cr.)
• When a clock pulse such as shown below is sent to pin CK, a short T2 prevents C2 voltage
from reaching the CK input threshold level ( 1.25V), and will cause a reset signal to be
output.
The T1 value can be found using the following formula :
T1 0.3 C2R2
T2
CK waveform
where VCC = 5V, T3 ≥ 3.0µsec, T2 ≥ 20µsec
T3
C2 voltage
T1
Example : Setting C and R allow the upper T1 value to be set (See the table below.)
C
R
T1
0.01µF
0.1µF
10kΩ
10kΩ
30µs
300µs
21
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