MB90495 Series
7. HANDLING DEVICES
(1) Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions:
A voltage higher than Vcc or lower than Vss is applied to an input or output pin.
A voltage higher than the rated voltage is applied between Vcc and Vss.
The AVcc power supply is applied before the Vcc voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the
device.
(2) Handling unused input pins
Do not leave unused input pins open, as doing so may cause misoperation of the device. Use a
pull-up or pull-down resistor.
(3) Using external clock
To use external clock, drive the X0 and X1 pins in reverse phase.
Below is a diagram of how to use external clock.
MB90495 Series
X0
X1
Figure 7.1 Using external clock
(4) Power supply pins (Vcc/Vss)
Ensure that all Vcc-level power supply pins are at the same potential. In addition, ensure the same
for all Vss-level power supply pins. (See the figure below.) If there are more than one Vcc or Vss
system, the device may operate incorrectly even within the guaranteed operating range. Note that
this product may not have as many power pins as pictured in the figure.
MB90495 Series Data Sheet (Advance Information)
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FME EMDC June 19, 2000
FUJITSU [ FUJITSU COMPONENT LIMITED. ]
