MB95120MB Series
(2) Source Clock/Machine Clock
(VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Value
Condi-
tion
Parameter
Symbol
Unit
Remarks
Min
Max
When using main clock
Min : FCH = 8.125 MHz,
PLL multiplied by 2
61.5
2000
ns
Source clock cycle time*1
(Clock before setting
division)
Max : FCH = 1 MHz, divided by 2
tSCLK
When using sub clock
Min : FCL = 32 kHz,
PLL multiplied by 4
7.6
61.0
μs
Max : FCL = 32 kHz, divided by 2
FSP
0.50
16.25 MHz When using main clock
Source clock frequency
⎯
FSPL
16.384 131.072 kHz When using sub clock
When using main clock
61.5
7.6
32000
976.5
ns Min : FSP = 16.25 MHz, no division
Max : FSP = 0.5 MHz, divided by 16
Machine clock cycle time*2
(Minimum instruction
execution time)
tMCLK
When using sub clock
μs Min : FSPL = 131 kHz, no division
Max : FSPL = 16 kHz, divided by 16
FMP
0.031
1.024
16.250 MHz When using main clock
131.072 kHz When using sub clock
Machine clock frequency
FMPL
*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This
source clock is divided by the machine clock division ratio selection bit (SYCC: DIV1 andDIV0) , and itbecomes
the machine clock. Further, the source clock can be selected as follows.
• Main clock divided by 2
• PLL multiplication of main clock (select from 1, 2, 2.5, 4 multiplication)
• Sub clock divided by 2
• PLL multiplication of sub clock (select from 2, 3, 4 multiplication)
*2 : Operation clock of the microcontroller. Machine clock can be selected as follows.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
• Outline of clock generation block
F
CH
Divided by 2
(main oscillation)
Main PLL
× 1
× 2
× 2.5
× 4
Division
circuit
× 1
SCLK
(source clock)
MCLK
(machine clock)
× 1/4
× 1/8
F
CL
Divided by 2
× 1/16
(sub oscillation)
Clock mode select bit
(SYCC: SCS1, SCS0)
Sub PLL
× 2
× 3
× 4
44
FUJITSU [ FUJITSU ]
