MB95120MB Series
The RP indicates the address of the register bank currently being used. The relationship between the content
of RP and the real address conforms to the conversion rule illustrated below:
• Rule for Conversion of Actual Addresses in the General-purpose Register Area
RP upper
OP code lower
"0" "0" "0" "0" "0" "0" "0" "1"
R4 R3 R2 R1 R0 b2
b1
b0
Generated address
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The DP specifies the area for mapping instructions (16 different instructions such as MOV A, dir) using direct
addresses to 0080H to 00FFH.
Direct bank pointer (DP2 to DP0)
Specified address area
Mapping area
0000H to 007FH (without mapping)
0080H to 00FFH (without mapping)
0100H to 017FH
XXXB (no effect to mapping)
0000H to 007FH
000B (initial value)
001B
010B
011B
100B
101B
110B
111B
0180H to 01FFH
0200H to 027FH
0080H to 00FFH
0280H to 02FFH
0300H to 037FH
0380H to 03FFH
0400H to 047FH
The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that
control CPU operations at interrupt.
H flag
I flag
Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.
Cleared to “0” otherwise. This flag is for decimal adjustment instructions.
Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”.
The flag is cleared to “0” when reset.
Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level
is higher than the value indicated by these bits.
:
:
:
IL1, IL0
IL1
0
IL0
0
Interrupt level
Priority
0
1
2
3
High
0
1
1
0
Low (no interruption)
1
1
N flag
Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Cleared to “0” when the
bit is set to “0”.
:
Z flag : Set to “1” when an arithmetic operation results in “0”. Cleared to “0” otherwise.
V flag
Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0”
otherwise.
:
C flag
Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared
to “0” otherwise. Set to the shift-out value in the case of a shift instruction.
:
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