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EDC1UV6414-70TG-S 参数 Datasheet PDF下载

EDC1UV6414-70TG-S图片预览
型号: EDC1UV6414-70TG-S
PDF下载: 下载PDF文件 查看货源
内容描述: [EDO DRAM Module, 1MX64, 70ns, CMOS, PDMA168]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 8 页 / 134 K
品牌: FUJITSU [ FUJITSU COMPONENT LIMITED. ]
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November 1996
Revision 1.1
EDC1UV641(1/4)-(60/70)(J/T)G-S
DC CHARACTERISTICS
(V
CC
= 3.3V±0.3V, V
SS
= 0V, T
A
= 0 to +70
°C)
60
Parameter
Symbol
Test Condition
Min.
Operating Current
I
CC1
RAS*, CAS* cycling; t
RC
= min.
LVTTL Interface
RAS*, CAS*
V
IH
D
out
= HIgh-Z
CMOS Interface
RAS*, CAS*
V
cc
- 0.2V
D
out
= HIgh-Z
RAS* -only Refresh
Current
CAS*-before-RAS*
Refresh Current
Hyper Page Mode
Current
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Notes:
1.
2.
3.
I
CC3
CAS*
V
IH
; RAS*, Address
cycling @ t
RC
= min.
RAS*, CAS* cycling @
t
RC
= min.
RAS*
V
IL
; CAS*, Address
cycling @ t
PC
= min.
0V
V
in
V
CC
+ 0.3V
0V
V
out
V
CC
D
out
= Disable
High I
out
= -2mA
Low I
out
= 2 mA
1KR
4KR
1KR
4KR
1KR
4KR
1KR
4KR
-
-
-
Max.
720
360
8
Min.
-
-
-
Max.
680
mA
320
8
mA
1, 2
70
Unit
Note
Standby current
I
CC2
-
-
-
-
-
-
-
-40
-10
2.4
0
4
720
360
680
360
440
360
40
10
-
0.4
-
-
-
-
-
-
-
-40
-10
2.4
0
4
680
mA
mA
320
640
mA
320
400
mA
320
40
10
-
0.4
2
I
CC4
I
CC5
I
LI
I
LO
V
OH
V
OL
1, 3
µ
A
µ
A
V
V
Values depend on output load condition when the device is selected. Maximum Values are specified at the output open condition.
Address can be changed once or less while RAS* = V
IL
.
Address can be changed once or less while CAS* = V
IH
.
CAPACITANCE
(TA =+25°C, V
CC
= 3.3V±0.3V)
Parameter
Input Capacitance (Address)
Input Capacitance (RAS*, OE*, WE*)
Input Capacitance (CAS0*~CAS7*)
Input/Output Capacitance (DQ0~DQ63)
Notes:
1.
2.
Symbol
C
I1
C
I2
C
I3
C
I/O
Max.
25
15
10
12
Unit
pF
pF
pF
pF
Note
1
1
1
1, 2
Capacitance is measured with Boonton Meter or effective capacitance method.
CAS* - V
IH
to disable D
out
.
4
Fujitsu Microelectronics, Inc.