Solid-State Fingerprint Sensor
After the row capture is completed, the High-Order Column Address
Register (CAH) and Low-Order Column Address Register (CAL)
must be programmed to select an element within the captured row to
be digitized. Writing to CAL causes the analog-to-digital (A/D)
converter to digitize the difference between the outputs of the two
sample-and-holds of the selected column cell. The output of the A/D
converter is accessed by reading the CAL register.
Rows can be accessed in any order; however, the selected row must be
captured before the column cells are read. The column cells within a
row can be accessed in any order.
Special Features
There are two programmable open-drain outputs that can be used
for driving LEDs.
The CLKOUT pin can be enabled to output a square-wave clock of
the same frequency as the oscillator clock. CLKOUT can be used to
drive external circuitry. When ENCLK is high, the clock signal is
present at the CLKOUT pin. When ENCLK is low or unconnected,
the CLKOUT output is held low.
MBF110 Pin Information for SOP (VSPA) 80/1
Pin
Number
34
35
36
37
38
39
40
17
18
19
21
22
24
25
26
27
32
31
15
Pin
Name
A3
A2
A1
A0
CE1
CE2
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
CLKOUT
ENCLK
LED1
Output
Input
Open-drain
Output
Open-drain
Output
Set Discharge Current
Input
Reserved pin
Digital Power Supply
Analog Power Supply
Must be left disconnected.
Place an external resistor R1 (200K – 680K ohms) between this pin and ground.
Typical: FPS110, R1 = 680K; FPS110B, R1 = 200K; FPS110E, R1 = 200K
LED driver
This pin can be used to drive an LED.
Clock Output
Enable Clock Output
This pin outputs the oscillator clock frequency when ENCLK is high.
A high on this pin enables the CLKOUT pin. A low on this pin holds CLKOUT low.
ENCLK has an internal pull-down resistor.
Bi-directional
Input
Type
Description
Notes
y
r
a
n
i
m
i
l
e
r
P
Address Inputs
Chip Enable, Active Low
Chip Enable, Active High
Read Enable, Active Low
Write Enable, Active Low
Data Bus
Address signals connected to these pins select a register to read from or write to dur-
ing data transfer.
When CE1 is low and CE2 is high, the chip is selected.
When CE1 is low and CE2 is high, the chip is selected.
This pin must be low while WR is high and the chip selected in order to read a register
on the chip.
This pin must be low while the chip is selected to write to a register on the chip.
Inputs when WR is low and chip is selected. Outputs when RD is low, WR is high, and
chip is selected.
14
3
2
13
20, 33
1
2
LED2
SETCUR
N/A
TEST
V
DD
V
DDA
Power
Fujitsu Microelectronics, Inc.
FUJITSU [ FUJITSU COMPONENT LIMITED. ]
