65nm CMOS Technology, CS200 / CS200A
Description
As miniaturization of silicon devices progresses,
Fujitsu provides the most competitive, world-class
technology to ASIC and COT customers. Fujitsu's
65nm technology has shrunk gates by 25% when
compared to the 90nm technology.
Fujitsu will start tape-out acceptance for the
technology in early 2006.
Features
•
The 30nm long gate, only 75% the size of the
CS100 transistors.
• 20 to 30% faster performance than the 90nm
generation.
• Transistor density doubled compared with the
90nm generation.
• SRAM cell area reduced 50% compared with the
90nm generation.
Specifications
65nm (CS200)
Gate length
Core VDD
Gate oxide thickness (physical)
Gate electrode
Source / drain electrode
Interconnects
Metal 1 pitch
Inter-level dielectric
Drain current enhancement
30nm
1.0V
1.1nm
NiSi / Poly-Si
NiSi
11-Cu + 1-Al
0.18µm
Porous ULK (k = 2.25)
Advanced stress control
65nm (CS200A)
50nm
1.2V
1.7nm
CoSi2 / Poly-Si
CoSi2
FUJITSU [ FUJITSU COMPONENT LIMITED. ]
