CS101 Series
■
AC CHARACTERISTICS
Parameter
Delay time
Symbol
tpd *
1
Value
Min
typ *
2
×
tmin *
3
Typ
typ *
2
×
ttyp *
3
Max
typ *
2
×
tmax *
3
Unit
ns
*1 : Delay time = propagation delay time, enable time, disable time
*2 : “typ” is calculated based on the cell specifications.
*3 : Measurement condition
Measurement condition
V
DD
=
1.2 V
±
0.1 V, V
SS
=
0 V, Tj
= −
40
°C
to
+125 °C
tmin
0.62
ttyp
1.00
tmax
1.57
Note : The values are reference values, which vary depending on the cells.
■
I/O PIN CAPACITANCE
Parameter
Input pin
Output pin
I/O pin
Symbol
C
IN
C
OUT
C
I/O
Value
Max16
Max16
Max16
Unit
pF
pF
pF
Note : The capacitance values vary depending on the package and pin positions.
■
DESIGN METHODS
Fujitsu Microelectronics’s Reference Design Flow provides the following functions that help shorten the devel-
opment time of large scale and high quality LSIs.
• High reliability design estimation in the early stage of physical design realized by physical prototyping.
• Layout synthesis with optimized timing realized by physical synthesis tools.
• High accuracy design environment considering drop in power supply voltage, signal noise, delay penalty, and
crosstalk.
• I/O design environment (power line design, assignment and selection of I/Os, package selection) considering
noise.
■
PACKAGES
Packages available for existing series can be used for CS101 series. This allows smooth replacement with
previously developed products.
Please contact your Fujitsu Microelectronics agent for details of delivery times.
FBGA package
PBGA package
TEBGA package
: Max 424 pins
: Max 420 pins
: Max 900 pins
FC-BGA package : Max 2116 pins
(Packages under planning are included.)
8
FUJITSU [ FUJITSU COMPONENT LIMITED. ]
