D A T A S H E E T
generated program pulses and verify the programmed
cell margin. Table 4 shows the address and data
requirements for the byte program command
sequence.
START
When the Embedded Program algorithm is complete,
the device then returns to reading array data and
addresses are no longer latched. The system can
determine the status of the program operation by using
DQ7 or DQ6. See “Write Operation Status” for informa-
tion on these status bits.
Write Program
Command Sequence
Data Poll
from System
Any commands written to the device during the
Embedded Program Algorithm are ignored. The Byte
Program command sequence should be reinitiated
once the device has reset to reading array data, to
ensure data integrity.
Embedded
Program
algorithm
in progress
Verify Data?
Yes
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1,” or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
No
No
Increment Address
Last Address?
Yes
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to
program bytes to the device faster than using the stan-
dard program command sequence. The unlock bypass
command sequence is initiated by first writing two
unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. The
device then enters the unlock bypass mode. A two-
cycle unlock bypass program command sequence is all
that is required to program in this mode. The first cycle
in this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. Table 4 shows the requirements for the
command sequence.
Programming
Completed
Note:See Table 4 for program command sequence.
Figure 1. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 4 shows
the address and data requirements for the chip erase
command sequence.
During the unlock bypass mode, only the Unlock
Bypass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset
command sequence. The first cycle must contain the
data 90h; the second cycle the data 00h. Addresses
are don’t cares for both cycles. The device then returns
to reading array data.
Any commands written to the chip during the
Embedded Erase algorithm are ignored. The Chip
Erase command sequence should be reinitiated once
the device has returned to reading array data, to
ensure data integrity.
Figure 1 illustrates the algorithm for the program oper-
ation. See the Erase/Program Operations table in “AC
Characteristics” for parameters, and to Figure 12 for
timing diagrams.
14
Am29LV010B
22140D6 October 11, 2006
FUJITSU [ FUJITSU ]
