FA531X series
■ Design advice
1. Startup circuit
It is necessary to start-up IC that the voltage inclination of
VCC terminal “dVcc/dt” satisfies the following equation(4).
dVcc/dt(V/s)>1.8/Cs(µF)...............................(4)
Cs : Capacitor connected between CS terminal and GND
Note that equation (4) must be satisfied in any condition. Also,
it is necessary to keep “latch mode” for overload protection or
overvoltage protection that the current supplied to VCC
terminal through startup resistor satisfies the following
equation(5).
Icc(Lat)> 0.4mA for Vcc Ϲ 9.2V ..................(5)
Icc(Lat) : Cutoff-state( = Latch mode ) supply current
The detail is explained as follows.
Fig. 20 Startup circuit example(1)
(1) Startup circuit connected to AC line directly
Fig. 20 shows a typical startup circuit that a startup
resistor Rc is connected to AC line directly. The period from
power-on to startup is determined by Rc, RD and CA. Rc, RD
and CA must be designed to satisfy the following equations.
dVcc/dt(V/s)=
(1/CA) • {(VAVE–Vccon )/RC–Vccon/RD–Iccst} >
1.8/(Cs(µF))................................................(6)
Rc(kΩ)< (VAVE–9.2(V))/{0.4 (mA) + (9.2(V)/RD(kΩ) } ...........(7)
VAVE = Vac •ǰ2/π : Average voltage applied to AC line side of Rc
Vac:
AC input effective voltage
Vccon: ON threshold of UVLO, 16.5V(max.) or 16.2V(max.)
Iccst: Standby current, 0.15 mA(max.)
In this method, Vcc voltage includes ripple voltage influenced
by AC voltage. Therefore, enough dVcc/dt required by
equation (6) tend to be achieved easily when Vcc reaches to
Vccon even if Vcc goes up very slowly. After power-off, Vcc
does not rise up because a voltage applied from bias winding
to VCC terminal decreases and the current flowing RC be-
comes zero, therefore, re-startup does not occur after Vcc falls
down below OFF threshold of UVLO until next power-on.
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FUJI [ FUJI ELECTRIC ]
